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([2a01:e0a:982:cbb0:3084:b2a4:688f:2d3a]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0f06deb8sm1885241766b.190.2025.01.03.06.49.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 03 Jan 2025 06:49:40 -0800 (PST) Message-ID: Date: Fri, 3 Jan 2025 15:49:39 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: Neil Armstrong Reply-To: neil.armstrong@linaro.org Subject: Re: [PATCH 0/2] arm64: dts: qcom: sm8650: rework CPU & GPU thermal zones To: Konrad Dybcio , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250103-topic-sm8650-thermal-cpu-idle-v1-0-faa1f011ecd9@linaro.org> Content-Language: en-US, fr Autocrypt: addr=neil.armstrong@linaro.org; keydata= xsBNBE1ZBs8BCAD78xVLsXPwV/2qQx2FaO/7mhWL0Qodw8UcQJnkrWmgTFRobtTWxuRx8WWP GTjuhvbleoQ5Cxjr+v+1ARGCH46MxFP5DwauzPekwJUD5QKZlaw/bURTLmS2id5wWi3lqVH4 BVF2WzvGyyeV1o4RTCYDnZ9VLLylJ9bneEaIs/7cjCEbipGGFlfIML3sfqnIvMAxIMZrvcl9 qPV2k+KQ7q+aXavU5W+yLNn7QtXUB530Zlk/d2ETgzQ5FLYYnUDAaRl+8JUTjc0CNOTpCeik 80TZcE6f8M76Xa6yU8VcNko94Ck7iB4vj70q76P/J7kt98hklrr85/3NU3oti3nrIHmHABEB AAHNKk5laWwgQXJtc3Ryb25nIDxuZWlsLmFybXN0cm9uZ0BsaW5hcm8ub3JnPsLAkQQTAQoA OwIbIwULCQgHAwUVCgkICwUWAgMBAAIeAQIXgBYhBInsPQWERiF0UPIoSBaat7Gkz/iuBQJk Q5wSAhkBAAoJEBaat7Gkz/iuyhMIANiD94qDtUTJRfEW6GwXmtKWwl/mvqQtaTtZID2dos04 YqBbshiJbejgVJjy+HODcNUIKBB3PSLaln4ltdsV73SBcwUNdzebfKspAQunCM22Mn6FBIxQ GizsMLcP/0FX4en9NaKGfK6ZdKK6kN1GR9YffMJd2P08EO8mHowmSRe/ExAODhAs9W7XXExw UNCY4pVJyRPpEhv373vvff60bHxc1k/FF9WaPscMt7hlkbFLUs85kHtQAmr8pV5Hy9ezsSRa GzJmiVclkPc2BY592IGBXRDQ38urXeM4nfhhvqA50b/nAEXc6FzqgXqDkEIwR66/Gbp0t3+r yQzpKRyQif3OwE0ETVkGzwEIALyKDN/OGURaHBVzwjgYq+ZtifvekdrSNl8TIDH8g1xicBYp QTbPn6bbSZbdvfeQPNCcD4/EhXZuhQXMcoJsQQQnO4vwVULmPGgtGf8PVc7dxKOeta+qUh6+ SRh3vIcAUFHDT3f/Zdspz+e2E0hPV2hiSvICLk11qO6cyJE13zeNFoeY3ggrKY+IzbFomIZY 4yG6xI99NIPEVE9lNBXBKIlewIyVlkOaYvJWSV+p5gdJXOvScNN1epm5YHmf9aE2ZjnqZGoM Mtsyw18YoX9BqMFInxqYQQ3j/HpVgTSvmo5ea5qQDDUaCsaTf8UeDcwYOtgI8iL4oHcsGtUX oUk33HEAEQEAAcLAXwQYAQIACQUCTVkGzwIbDAAKCRAWmrexpM/4rrXiB/sGbkQ6itMrAIfn M7IbRuiSZS1unlySUVYu3SD6YBYnNi3G5EpbwfBNuT3H8//rVvtOFK4OD8cRYkxXRQmTvqa3 3eDIHu/zr1HMKErm+2SD6PO9umRef8V82o2oaCLvf4WeIssFjwB0b6a12opuRP7yo3E3gTCS KmbUuLv1CtxKQF+fUV1cVaTPMyT25Od+RC1K+iOR0F54oUJvJeq7fUzbn/KdlhA8XPGzwGRy 4zcsPWvwnXgfe5tk680fEKZVwOZKIEuJC3v+/yZpQzDvGYJvbyix0lHnrCzq43WefRHI5XTT QbM0WUIBIcGmq38+OgUsMYu4NzLu7uZFAcmp6h8g Organization: Linaro In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 03/01/2025 15:43, Konrad Dybcio wrote: > On 3.01.2025 3:38 PM, Neil Armstrong wrote: >> On the SM8650 platform, the dynamic clock and voltage scaling (DCVS) for >> the CPUs and GPU is handled by hardware & firmware using factory and >> form-factor determined parameters in order to maximize frequency while >> keeping the temperature way below the junction temperature where the SoC >> would experience a thermal shutdown if not permanent damages. >> >> On the other side, the High Level Ooperating System (HLOS), like Linux, >> is able to adjust the CPU and GPU frequency using the internal SoC >> temperature sensors (here tsens) and it's UP/LOW interrupts, but it >> effectly does the same work twice in an less effective manner. >> >> Let's take the Hardware & Firmware action in account and design the >> thermal zones trip points and cooling devices mapping to use the HLOS >> as a safety warant in case the platform experiences a temperature surge >> to helpfully avoid a thermal shutdown and handle the scenario gracefully. >> >> On the CPU side, the LMh hardware does the DCVS control loop, so >> let's set higher trip points temperatures closer to the junction >> and thermal shutdown temperatures and add some idle injection cooling >> device with 100% duty cycle for each CPU that would act as emergency >> action to avoid the thermal shutdown. >> >> On the GPU side, the GPU Management Unit (GMU) acts as the DCVS >> control loop, but since we can't perform idle injection, let's >> also set higher trip points temperatures closer to the junction >> and thermal shutdown temperatures to reduce the GPU frequency only >> as an emergency action before the thermal shutdown. >> >> Those 2 changes optimizes the thermal management design by avoiding >> concurrent thermal management, calculations & avoidable interrupts >> by moving the HLOS management to a last resort emergency if the >> Hardware & Firmwares fails to avoid a thermal shutdown. >> >> Signed-off-by: Neil Armstrong >> --- > > Got any numbers to back this? To back which part ? Yes I've been running loads with difference scenarios and effectively the hardware work is much better with a more linear correction and slighly better performances because it sets slighly higger OPPs while maintaining the core closer to the target temperature range. Which is kind of expected. I don't have easy numbers to share, sorry... So yes I consider avoiding the concurrent effort is better, but since we also take the firmware design in account in the whole platform representation in DT (DSPs, SCM, GMU, ...) we should also extend this to thermal. Neil > > Konrad