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X-CSE-ConnectionGUID: Wy9RbGzWS2q6EG8bJXxL7Q== X-CSE-MsgGUID: eA7+tcrvTCiNDaaCT8jRHg== X-IronPort-AV: E=McAfee;i="6700,10204,11363"; a="42216272" X-IronPort-AV: E=Sophos;i="6.14,220,1736841600"; d="scan'208";a="42216272" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2025 07:09:56 -0800 X-CSE-ConnectionGUID: Sg0R8AiqRrqT13SZRdhoQA== X-CSE-MsgGUID: WdUDCJMiSBafbrn400eNuQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,220,1736841600"; d="scan'208";a="118404768" Received: from kinlongk-desk.amr.corp.intel.com (HELO [10.125.109.94]) ([10.125.109.94]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2025 07:09:54 -0800 Message-ID: Date: Tue, 4 Mar 2025 07:10:13 -0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v14 03/13] x86/mm: add INVLPGB support code To: Borislav Petkov Cc: Rik van Riel , x86@kernel.org, linux-kernel@vger.kernel.org, peterz@infradead.org, dave.hansen@linux.intel.com, zhengqi.arch@bytedance.com, nadav.amit@gmail.com, thomas.lendacky@amd.com, kernel-team@meta.com, linux-mm@kvack.org, akpm@linux-foundation.org, jackmanb@google.com, jannh@google.com, mhklinux@outlook.com, andrew.cooper3@citrix.com, Manali.Shukla@amd.com, mingo@kernel.org References: <20250226030129.530345-1-riel@surriel.com> <20250226030129.530345-4-riel@surriel.com> <20250228194734.GGZ8IS1iFVpPzmEyYl@fat_crate.local> <30c721e0-338d-4172-989c-5226d584bcbc@intel.com> <34b80474-a309-493b-81e9-3a7d4de8a369@intel.com> <20250304110032.GEZ8bdUOg2WLUrhMcm@fat_crate.local> From: Dave Hansen Content-Language: en-US Autocrypt: addr=dave.hansen@intel.com; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 3/4/25 03:00, Borislav Petkov wrote: > On Mon, Mar 03, 2025 at 11:23:58AM -0800, Dave Hansen wrote: >> Here's a plain diff if you just want to squish it in. > >> diff --git a/arch/x86/include/asm/tlb.h b/arch/x86/include/asm/tlb.h >> index 5375145eb9596..3bd617c204346 100644 >> --- a/arch/x86/include/asm/tlb.h >> +++ b/arch/x86/include/asm/tlb.h >> @@ -28,6 +28,11 @@ static inline void invlpg(unsigned long addr) >> asm volatile("invlpg (%0)" ::"r" (addr) : "memory"); >> } >> >> +enum invlpgb_stride { > > Right, this is an address stride, as the text calls it. > >> + NO_STRIDE = 0, >> + PTE_STRIDE = 0, > > Ok, so those are confusing. No stride is PTE stride so let's just zap > NO_STRIDE. Passing "PTE_STRIDE" to an operation that doesn't have a stride is pretty confusing too. ... > /* Flush all mappings, including globals, for all PCIDs. */ > @@ -117,21 +126,21 @@ static inline void invlpgb_flush_all(void) > * as it is cheaper. > */ > guard(preempt)(); > - __invlpgb(0, 0, 0, 1, 0, INVLPGB_INCLUDE_GLOBAL); > + __invlpgb(0, 0, 0, 1, PTE_STRIDE, INVLPGB_FLAG_INCLUDE_GLOBAL); > __tlbsync(); > } This one, for example. It's not flushing PTEs an doesn't have a start address or nr>0. So, we could have the enum be totally divorced from the hardware type: NO_STRIDE, PTE_STRIDE, PMD_STRIDE and decode it at the end: if (stride == PMD_STRIDE) foo | PMD_STRIDE_BIT;