From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from vps0.lunn.ch (vps0.lunn.ch [156.67.10.101]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AB9F41E3DFE; Thu, 16 Jan 2025 13:06:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=156.67.10.101 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737032793; cv=none; b=bhBioYoH5ZLTNK6EmNzb6qzYyEhd/BHT4+eFskpzfvYRujQ3Asy/vsg93U4IH04N9OuL6LJ2O6JVxEJHycDRbi+zFSoYMevI0GuVQr+Fwdmc4l3TS+T4GcdRsFopdZK9UIHqWxQZaduzKgugzT8c30xYCk9zHIoS4ItKjyV9At4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737032793; c=relaxed/simple; bh=OnXHaP2RXlZAkdXMUBJaRh3PdILLHIcuTgCimQm/K60=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=UNVLywDsnCv3D8sbQoSxjc9X9aMVDKPDk8BxhiQuSvZiD2KN+Dnxd+YEZJ0RP3tBz8vxCNMdjhjd+dPq8j9mMuvbxbZllCqwdEdm8R7ajL7CHkIpWL4JSIv7BW8jN4MlftwItxzrJcLSgqn/i8AE7jXFSJRM9j/je7MYHD6r2Xk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=lunn.ch; spf=pass smtp.mailfrom=lunn.ch; dkim=pass (1024-bit key) header.d=lunn.ch header.i=@lunn.ch header.b=Jm5IRekK; arc=none smtp.client-ip=156.67.10.101 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=lunn.ch Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=lunn.ch Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=lunn.ch header.i=@lunn.ch header.b="Jm5IRekK" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=In-Reply-To:Content-Disposition:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:From:Sender:Reply-To:Subject: Date:Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding: Content-ID:Content-Description:Content-Disposition:In-Reply-To:References; bh=gGfqbH0+0xNHDaBP8mufxix1MaSaVnHOZLrK9FPiOgQ=; b=Jm5IRekKNfHpSJBpdovOOR/X1F 4+XkY+5vrPKiy+RrkNFrHkKkTjTjoRvdjg4/yvV1XYGXoKssZR5dmsKu+ETY7/iyTBEP9HUbv9Osw aHI75CwnRw4gHylFHvU19qv8uLWj8vGGBszWxxdCStfdnU8NTLo5S6jeGQhNpTX2tBpk=; Received: from andrew by vps0.lunn.ch with local (Exim 4.94.2) (envelope-from ) id 1tYPZX-00582T-GD; Thu, 16 Jan 2025 14:06:07 +0100 Date: Thu, 16 Jan 2025 14:06:07 +0100 From: Andrew Lunn To: Marek Vasut Cc: netdev@vger.kernel.org, "David S. Miller" , Eric Dumazet , Heiner Kallweit , Jakub Kicinski , Paolo Abeni , Russell King , Tristram Ha , UNGLinuxDriver@microchip.com, Vladimir Oltean , Woojung Huh , linux-kernel@vger.kernel.org Subject: Re: [net-next,PATCH 1/2] net: dsa: microchip: Add emulated MIIM access to switch LED config registers Message-ID: References: <20250113001543.296510-1-marex@denx.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250113001543.296510-1-marex@denx.de> > This preparatory patch exposes the LED control bits in those Switch Config > Registers by mapping them at high addresses in the MIIM space, so the PHY > driver can access those registers and surely not collide with the existing > MIIM block registers. The two registers which are exposed are the global > Register 11 (0x0B): Global Control 9 as MIIM block register 0x0b00 and > port specific Register 29/45/61 (0x1D/0x2D/0x3D): Port 1/2/3 Control 10 > as MIIM block register 0x0d00 . The access to those registers is further > restricted only to the LED configuration bits to prevent the PHY driver > or userspace tools like 'phytool' from tampering with any other switch > configuration through this interface. I do wounder about using register numbers outside of the 0-31 range. We never have enforced it, but these clearly break 802.3 C22. I wounder if it would be better to emulate pages as well. The PHY driver already has lanphy_write_page_reg() and lanphy_read_page_reg(). Could you emulate what those need? It adds a lot of complexity, but it should be future proof. What might be simpler is to expose an emulated C45 register range, and put the registers in the vendor section. Andrew