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From: Dmitry Osipenko <digetx@gmail.com>
To: Thierry Reding <thierry.reding@gmail.com>,
	Jonathan Hunter <jonathanh@nvidia.com>
Cc: "Rob Herring" <robh+dt@kernel.org>,
	"Andreas Färber" <afaerber@suse.de>,
	devicetree@vger.kernel.org, linux-tegra@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: [PATCH v2 1/2] ARM: dts: tegra30: Add IRAM node
Date: Sun, 18 Feb 2018 22:46:55 +0300	[thread overview]
Message-ID: <eca7e53ced963c97e3363d7598fe3778f35e79f2.1518981147.git.digetx@gmail.com> (raw)
In-Reply-To: <cover.1518981147.git.digetx@gmail.com>
In-Reply-To: <cover.1518981147.git.digetx@gmail.com>

IRAM is a static RAM that consists of four contiguous 64 KiB blocks,
it is currently used to store CPU resume code, utilized by the video
decoder engine and could be used as a general-purpose fast memory.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
 arch/arm/boot/dts/tegra30.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index c3e9f1e847db..833d97206aef 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -91,6 +91,14 @@
 		};
 	};
 
+	iram@40000000 {
+		compatible = "mmio-sram";
+		reg = <0x40000000 0x40000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x40000000 0x40000>;
+	};
+
 	host1x@50000000 {
 		compatible = "nvidia,tegra30-host1x", "simple-bus";
 		reg = <0x50000000 0x00024000>;
-- 
2.16.1

  reply	other threads:[~2018-02-18 19:48 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-02-18 19:46 [PATCH v2 0/2] Enable Video Decoder on Tegra30 Dmitry Osipenko
2018-02-18 19:46 ` Dmitry Osipenko [this message]
2018-02-18 19:46 ` [PATCH v2 2/2] ARM: dts: tegra30: Add video decoder node Dmitry Osipenko
2018-03-08 14:00 ` [PATCH v2 0/2] Enable Video Decoder on Tegra30 Thierry Reding

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