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Fri, 29 May 2026 01:42:07 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA05.qualcomm.com (8.18.1.7/8.18.1.7) with ESMTPS id 64T1g6LA021337 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 29 May 2026 01:42:06 GMT Received: from [10.233.71.148] (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Thu, 28 May 2026 18:42:03 -0700 Message-ID: Date: Fri, 29 May 2026 09:42:02 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v9 3/4] coresight: cti: add Qualcomm extended CTI identification and quirks To: Leo Yan , Yingchao Deng CC: Suzuki K Poulose , Mike Leach , James Clark , "Alexander Shishkin" , , , , , , , , Yingchao Deng References: <20260521-extended_cti-v9-0-d21f4f92c51e@oss.qualcomm.com> <20260521-extended_cti-v9-3-d21f4f92c51e@oss.qualcomm.com> <20260528171108.GI101133@e132581.arm.com> Content-Language: en-US From: "Yingchao Deng (Consultant)" In-Reply-To: <20260528171108.GI101133@e132581.arm.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-GUID: y5BtHFN8JWbc4RbAPU7bY33Ai4q1piQ5 X-Proofpoint-ORIG-GUID: y5BtHFN8JWbc4RbAPU7bY33Ai4q1piQ5 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTI5MDAxMyBTYWx0ZWRfXxEsgedwBl2/4 XcW6fn2BpZHrf/jB0lxGSCZ1LDyTpg0DpSioduzSamitV5f1Qd1rz2h1n7OChjXmaljQ6YC172C t5zthLDkrtwt1oMQ+uX4hctWKZjNcFCOgxVtSPcgIRZ72yucsNyx115cVeriDGGmdxpl716+w7a r9loeoH4z5dhKFvCSg9hJJrFGJTOrXpSoXTr9zbimSre3x1XdvG1Lk5T4+jZ1076HYhy+czjHQK GeTZ4lH+/9F8IbLhBAoBFbSua/FlaQrPxnvHOpPsDHELspvXYy4TjnYLfVgyJVoC8HmDncC3V3O KHNcaSEBt/lJt7LJMhLP3zdVv826P4iCLueoy/NTC2ai7m57nUd5lP3EqNFZxN+Aji3q2Nqq9n7 JTjvd1hc68FbHJnkdk0BR7tXttfcwDAHYkVfJbOSC5aZYKhbh/P711amDqOz+euj5wL8MEtjdd+ vcBedUk/Y0xONUDG6dg== X-Authority-Analysis: v=2.4 cv=cObQdFeN c=1 sm=1 tr=0 ts=6a18eeef cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=ISzTLn2FSy6o0I3Y5eYA:9 a=QEXdDO2ut3YA:10 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-05-28_07,2026-05-28_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 clxscore=1015 spamscore=0 malwarescore=0 phishscore=0 suspectscore=0 priorityscore=1501 lowpriorityscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2605290013 On 5/29/2026 1:11 AM, Leo Yan wrote: > On Thu, May 21, 2026 at 08:16:29PM +0800, Yingchao Deng wrote: > > [...] > >> Qualcomm implements an extended variant of the ARM CoreSight CTI with a >> different register layout and vendor-specific behavior. While the >> programming model remains largely compatible, the register offsets differ >> from the standard ARM CTI and require explicit handling. > I cannot apply this patch successfuly. Please rebase on the latest > coresight-next branch. > >> @@ -726,6 +734,22 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id) >> >> raw_spin_lock_init(&drvdata->spinlock); >> >> + devarch = readl_relaxed(drvdata->base + CORESIGHT_DEVARCH); >> + if (CTI_DEVARCH_ARCHITECT(devarch) == ARCHITECT_QCOM) { >> + drvdata->is_qcom_cti = true; >> + /* >> + * QCOM CTI does not implement Claimtag functionality as >> + * per CoreSight specification, but its CLAIMSET register >> + * is incorrectly initialized to 0xF. This can mislead >> + * tools or drivers into thinking the component is claimed. >> + * >> + * Reset CLAIMSET to 0 to reflect that no claims are active. >> + */ >> + CS_UNLOCK(drvdata->base); >> + writel_relaxed(0, drvdata->base + CORESIGHT_CLAIMSET); >> + CS_LOCK(drvdata->base); > Sorry I missed this piece before. > > Can you move this quirk into firmware? I don't think the CTI driver > should clear the external claim bit as this totally break the protocol > defined in PSCI. A clean way would clear the bits in firmware and then > CTI driver can use the CLAIM registers. > > Or, another option is to create several helpers to bypass claim > operations for Qcom CTI: > > static void cti_clear_self_claim_tag(cti_drvdata *drvdata, > struct csdev_access *csa) > { > if (drvdata->is_qcom_cti) > return; > > coresight_clear_self_claim_tag(csa); > } > > static int cti_claim_device(cti_drvdata *drvdata) > { > if (drvdata->is_qcom_cti) > return 0; > > return coresight_claim_device(drvdata->csdev); > } > > static void cti_unclaim_device_unlocked(cti_drvdata *drvdata) > { > if (drvdata->is_qcom_cti) > return; > > return coresight_disclaim_device_unlocked(drvdata->csdev); > } > > Otherwise, this patch is fine for me. > > Thanks, > Leo Thanks for the suggestion. Moving this to firmware would be ideal, but in our case this behavior comes from the hardware design and affects multiple platforms, so it is not something we can easily address in firmware. I will go with the helper bypass approach. Thanks, Yingchao