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Mon, 11 Aug 2025 22:05:36 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFp8q7iEcoE6icwUvjRib+HG6J9UgPT0yWBcxWWwYRBGOzentck67PNXD0Zcb1/vkf9fjph/A== X-Received: by 2002:a17:902:f68c:b0:240:900b:7550 with SMTP id d9443c01a7336-242fc21006fmr28005135ad.5.1754975136011; Mon, 11 Aug 2025 22:05:36 -0700 (PDT) Received: from [10.217.217.159] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-24304c2943asm373085ad.30.2025.08.11.22.05.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 11 Aug 2025 22:05:35 -0700 (PDT) Message-ID: Date: Tue, 12 Aug 2025 10:35:30 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/3] clk: qcom: dispcc-sc7280: Add dispcc resets To: Bjorn Andersson , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org, Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250811-sc7280-mdss-reset-v1-0-83ceff1d48de@oss.qualcomm.com> <20250811-sc7280-mdss-reset-v1-2-83ceff1d48de@oss.qualcomm.com> Content-Language: en-US From: Taniya Das In-Reply-To: <20250811-sc7280-mdss-reset-v1-2-83ceff1d48de@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODExMDEwNyBTYWx0ZWRfX+Slk5OCv+gnC +MV3BXO2K7TxEvwWlP5sT1gXvs79rdDT6wUJlJGivE9EcIUWwhuGeEbJRoONzB//rL11JkzUpR1 ItfXhc9/E6rBkob83ngiFuGh0A1uKaDV0e9HymQqktntlgp/reFv2pBj/TGKy7acg/aSSKNXfsY 5+OUOYW7GE7wtoV2HCPuMcellsu4Sc4y+Vun1nS0AtEE60V03GLVydXFOpqv9cMXWXvgE6YZ1bC 6+zLhTzpatvmo3ydriIAUC2Tk+m8XutTOQco+pFSYtHQt957WuiOYHmMM6poqIvEbM1u3ry88jg XOpO3fdIKN37+MST8sguAsAgRP0rvm7YV/JwML/3a8ElQOOzRnVfPkCbc84oP+h9jwJV0UexU6j UHW80B6p X-Proofpoint-GUID: 5E1WP46PcLADdahptWcjXjKMyAE3iFim X-Authority-Analysis: v=2.4 cv=A+1sP7WG c=1 sm=1 tr=0 ts=689acba1 cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=EUspDBNiAAAA:8 a=NNVWRqRCdYL-THHIErAA:9 a=QEXdDO2ut3YA:10 a=_Vgx9l1VpLgwpw_dHYaR:22 X-Proofpoint-ORIG-GUID: 5E1WP46PcLADdahptWcjXjKMyAE3iFim X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-12_01,2025-08-11_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 priorityscore=1501 malwarescore=0 spamscore=0 phishscore=0 clxscore=1015 adultscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508110107 On 8/12/2025 8:41 AM, Bjorn Andersson wrote: > Like many other platforms the sc7280 display clock controller provides > a couple of resets for the display subsystem. In particular the > MDSS_CORE_BCR is useful to reset the display subsystem to a known state > during boot, so add these. > In this issue I believe the requirement is to have a clean sheet and restart the MDSS explicitly. Historically MDSS never required a BCR reset. > Signed-off-by: Bjorn Andersson > --- > drivers/clk/qcom/dispcc-sc7280.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/drivers/clk/qcom/dispcc-sc7280.c b/drivers/clk/qcom/dispcc-sc7280.c > index 8bdf57734a3d47fdf8bd2053640d8ef462677556..465dc06c87128182348a4e0ea384af779647bd84 100644 > --- a/drivers/clk/qcom/dispcc-sc7280.c > +++ b/drivers/clk/qcom/dispcc-sc7280.c > @@ -17,6 +17,7 @@ > #include "clk-regmap-divider.h" > #include "common.h" > #include "gdsc.h" > +#include "reset.h" > > enum { > P_BI_TCXO, > @@ -847,6 +848,11 @@ static struct gdsc *disp_cc_sc7280_gdscs[] = { > [DISP_CC_MDSS_CORE_GDSC] = &disp_cc_mdss_core_gdsc, > }; > > +static const struct qcom_reset_map disp_cc_sc7280_resets[] = { > + [DISP_CC_MDSS_CORE_BCR] = { 0x1000 }, > + [DISP_CC_MDSS_RSCC_BCR] = { 0x2000 }, > +}; > + > static const struct regmap_config disp_cc_sc7280_regmap_config = { > .reg_bits = 32, > .reg_stride = 4, > @@ -861,6 +867,8 @@ static const struct qcom_cc_desc disp_cc_sc7280_desc = { > .num_clks = ARRAY_SIZE(disp_cc_sc7280_clocks), > .gdscs = disp_cc_sc7280_gdscs, > .num_gdscs = ARRAY_SIZE(disp_cc_sc7280_gdscs), > + .resets = disp_cc_sc7280_resets, > + .num_resets = ARRAY_SIZE(disp_cc_sc7280_resets), > }; > > static const struct of_device_id disp_cc_sc7280_match_table[] = { > Reviewed-by: Taniya Das -- Thanks, Taniya Das