From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0AE6926E703; Mon, 4 Aug 2025 14:19:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754317159; cv=none; b=RmmKO/JRFu2dsdb7mzaro81EJPLf5ugqJzfwdrXAjuxWAV40yQQqvkKJAB48RodronxA/NPjbqF3Horp+qLbW0wrVp7ebF1C4MXMj1jxoSiOL6zaK2jhYMCnAOMywSVPCecl838mQClyyoGqK8xzZjwRcmdUCZOxRPrMt9VaA/U= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754317159; c=relaxed/simple; bh=SjJSeEYpC8XNqF4m5DqAU8lWdtGSO9pN6bQ0yYPAzdk=; h=Message-ID:Date:MIME-Version:Subject:From:To:Cc:References: In-Reply-To:Content-Type; b=m0ZxkO5NfBZTjnAJIMjbNcaAYjfYr52cm3CdsVIrB5GQ9o+92Jbshqu+8Vgw9nTIBEwiUWYm7RwJGA9HVn9CZkqNR7pncMX0LjZ9lSjOQJpSnYc4SOSETAt9ACdzHlycYRqNvUK0Q8Q3pl0fdaDSjBNX6hnW/HGvt8/WRi5pp8c= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=deNP3Dnv; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="deNP3Dnv" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5DA74C4CEE7; Mon, 4 Aug 2025 14:19:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1754317156; bh=SjJSeEYpC8XNqF4m5DqAU8lWdtGSO9pN6bQ0yYPAzdk=; h=Date:Subject:From:To:Cc:References:In-Reply-To:From; b=deNP3DnvHkJ2HSq68I0MNQfdiri4MkDm0lE+b0b8Haf2PfDnyij9j9+1u7N/dfglh W9yspUm5bXEPmtZn4P5v7oZfotQYBFZJEOTWN7LmaxUFiYiVlmjPvlGrBtGbR7i3WZ h5l/D4BSA5CkbXtc9WCfSk65924x71zlAxEmZFwp+EefKY0LctMis4XlgU3mOHVQ/9 rvFzE3en6MYB9P1VytSn6hdgnyeVKcvjfoHHKTd55Dz9uCtpJtREqRpAvS0JKErgUm s/ODUfZdbeIeoPmq5LcB7DN25ZWTm4RphbTrZBeBGzTrIgkQ3gkz8VpdzqfpKyhWt4 jXaTfTuM8ogPg== Message-ID: Date: Mon, 4 Aug 2025 16:19:10 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 09/27] dt-bindings: clock: mediatek: Describe MT8196 clock controllers From: Krzysztof Kozlowski To: AngeloGioacchino Del Regno , Laura Nao , wenst@chromium.org Cc: conor+dt@kernel.org, devicetree@vger.kernel.org, guangjie.song@mediatek.com, kernel@collabora.com, krzk+dt@kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, matthias.bgg@gmail.com, mturquette@baylibre.com, netdev@vger.kernel.org, nfraprado@collabora.com, p.zabel@pengutronix.de, richardcochran@gmail.com, robh@kernel.org, sboyd@kernel.org References: <20250804083540.19099-1-laura.nao@collabora.com> <373f44c3-8a6a-4d52-ba6b-4c9484e2eac1@kernel.org> <1db77784-a59a-49bd-89b5-9e81e6d3bafc@collabora.com> <00a12553-b248-4193-8017-22fea07ee196@collabora.com> <2555e9fe-3bc0-4f89-9d0b-2f7f946632e7@kernel.org> Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 04/08/2025 15:58, Krzysztof Kozlowski wrote: >> >> So, what should we do then? >> >> Change it to "mediatek,clock-hw-refcounter", and adding a comment to the binding >> saying that this is called "Hardware Voter (HWV)" in the datasheets? >> >> Or is using the "interconnect" property without any driver in the interconnect API >> actually legit? - Because to me it doesn't look like being legit (and if it is, it >> shouldn't be, as I'm sure that everyone would expect an interconnect API driver >> when encountering an "interconnect" property in DT), and if so, we should just add > > Why you would not add any interconnect driver for interconnect API? > Look, the current phandle allows you to poke in some other MMIO space > for the purpose of enabling the clock FOO? So interconnect or power > domains or whatever allows you to have existing or new driver to receive > xlate() and, when requested resources associated with clock FOO. Something got here cut. Last sentence is supposed to be: "So interconnect or power domains or whatever allows you to have existing or new driver to receive xlate() and, when requested, toggle the resources associated with clock FOO." > > Instead of the FOO clock driver poking resources, you do > clk_prepare_enable() or pm_domain or icc_enable(). I looked now at the driver and see your clock drivers poking via regmap to other MMIO. That's exactly usecase of syscon and exactly the pattern *we are usually discouraging*. It's limited, non-scalable and vendor-driven. If this was a power domain provider then: 1. Your clock drivers would only do runtime PM. 2. Your MCU would be the power domain controller doing whatever is necessary - toggling these set/clr bits - when given clock is enabled. And it really looks like what you described... Best regards, Krzysztof