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Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH] accel/amdxdna: Clear mailbox interrupt register during channel creation Content-Language: en-US To: "Falkowski, Maciej" , , , CC: , , , References: <20251107181115.1293158-1-lizhi.hou@amd.com> <3ee3c7a6-65cc-4d67-9a4d-5b9b09e7908e@linux.intel.com> From: Lizhi Hou In-Reply-To: <3ee3c7a6-65cc-4d67-9a4d-5b9b09e7908e@linux.intel.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9CD:EE_|CH3PR12MB9250:EE_ X-MS-Office365-Filtering-Correlation-Id: 0cc0f911-ee39-4a00-1de9-08de22d33441 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|1800799024|376014|7053199007; X-Microsoft-Antispam-Message-Info: =?utf-8?B?ZFZhWmE1L3NHNjl2K01lZW1NdUZjVmIyRG1VVEZXNU1pTnVpNWF4RmVNY1px?= =?utf-8?B?SjdXZXZyRXFaS2pVMnB3UG9HVEcwSysydGZJays0NkxUaWxWNitxV2N3Viti?= =?utf-8?B?eEZHbDVlSll2MGlMS3JHM3ZBUGRtcmhxU295TmpZSVhIUkIxNmVPcG5henJS?= =?utf-8?B?L0g2anJGUjNrODk5Z2hZZEJ2TTlzeXBhUzZ2bHZtSnBGOU93Y3FLdVRZb29U?= =?utf-8?B?QU4yWmJpV25PZDJiYkx0T2hHNitQTFZKRTUzQU5uT2ZJT01KZElVMXR3TVBB?= =?utf-8?B?ek82Y2FmRDZWSmcycHV0alpmYW1IRDZNSGlaUjFhVEpNd09pR2VweHcwdWlu?= =?utf-8?B?ZFZBc0lvWXE5aEV5bjdHT0lHTVpIbkxhRERGRjNOWXFST3BxMyt6N0tLdFp1?= =?utf-8?B?WG1GaHNjZU9vUk5YRUdtdGY2bjU2Q3FPMDlOOTF3cmY4aXhYWEpWa3VNaENR?= =?utf-8?B?WXVVU1JRWThjMTByRU1hNENJVE5qZXFrV1dRRld3eG5ISUx5TkxWYjdVWTRr?= =?utf-8?B?ZWkvcGRiRHFod0pXUXJjdjdONUo5ZG9KUlZwSHo0NXFnVk5KbHlRd1JGNHhK?= =?utf-8?B?d0FwZmVYVmdDdFJLUG92ZFhNUTdMQ0RrR1FqWm16ZFZXeUs1M3UvMzRNTkov?= =?utf-8?B?TFdoZktRbHRzL0J2d0VKTU5ycXhjVFB6eGRqbTliNHB4eHlKNVZoQitsNGIz?= =?utf-8?B?WHFCdkdmbXorTVJjWjR5YjVEbGsydDQ5bk52NXRVSlNzYnFBMHNDM3JjSWIw?= =?utf-8?B?dlNFbVhvT3ExZWRNVmVRTDdVL09GMmxuWkhtNm5KdllHa3JQL0lYejZJSmlH?= =?utf-8?B?T2hCb2FOSENoNXNtMjExM1F3dHVEQ21meEZmQ3BTYnpxdEozekNkYktFZStq?= =?utf-8?B?SlNsQmowUW51V09XRU1OeWlLQjZ5N2pqeDhNQm1PQWtqNC91M3VKNXI3WGIx?= =?utf-8?B?WUU4S0pMYWdLQmR2Ukt3K2c5VjRvbFpOTmtlY1hnR0x1blVzTi80a2NvaG1u?= =?utf-8?B?MXJlalk1QVd6dXA2aC9XZVBLVzc3UU1yUjdiK2F3NGNmaTlYaFAwMlVwQm9G?= =?utf-8?B?UG5tQWM4bU1uM0xhWDl4RkpoMDB5RnZ1UlgxREFYVlVlR3phaGpJdnpXTk9H?= =?utf-8?B?ZVdKMFljajB1L3E3Mjl1ZUxBVnlJbmhIKy9HRk9tZk9tWHJORllrN2hkN3Nt?= =?utf-8?B?MTF4QlFLK3JwU21RNmxJdXRZUTFmSXdEOHpDZ25WSTRzWDNQNDc1KzUrTnFr?= =?utf-8?B?a0duVGdjUGpoL0tIaUtqVXNRVTFINXdQRnJuQ09WTVNRY3BxejIzR0M3OE50?= =?utf-8?B?a0NQUEJzY1RYL1JjTk4yVGJVWm83c3p2dDMrOFc1dHdnSWdTQUdtQUZmTXFa?= =?utf-8?B?OWM2VHVmaTNjZStiWHNTbk1xR1Y1RHJZZXVGYWw1UmJjTlNTTjdGNEtlZWxz?= =?utf-8?B?T2hiU1JsUFBOSURoc29KWktSQ2pScDlZZXJTYTZjejFxRmpWMlpiQ1FHTG5n?= =?utf-8?B?SlRMVTByR1Q4ZXhxQitHU3BkNk91dkJDeHd3dXFKRWpvcmJ4NVdsNThueGl1?= =?utf-8?B?MjB2VFhaMUVER2N3bTgxazFFTUZNTnNBTXpYYjMyRnp2REtxVWNxR2J3Ym9z?= =?utf-8?B?YzBwSzZtaGpQeEhCNTdJWDhRalV4ZE15Zzc5YjRhcEJmeVlhNndoSjFlRlU4?= =?utf-8?B?NmFrWkJsSXFUaG9GQkZwSVdnR1F6OHZ6R0c2NnIvQ1ZoSFVZdjZMNkJuTEJo?= =?utf-8?B?ZDJxNVBpZS94cWVwclVDcGFUUnJEUDhBYklqTFA5cDVsaTd3VTZJc3Q3SEE0?= =?utf-8?B?UkNVZTN2cDR5dXRDcTBEQnF0TjB6VEo1d1o2aWZLNEpVUVJCa0ZrOVJwWk5m?= =?utf-8?B?eVBjQ3ZGL0xDSEhsSzhkT0oyaGlGVy80bzExWFoyZGVaNjVZdkQ4VVkxdzFZ?= =?utf-8?B?a3gzOWZ2Rm5uakc4T0lhWXZwMFFYVG5mZkx4VW92THQwV2xLWS8yNU5NKzcx?= =?utf-8?B?VnhQS08vTHBwZTRud1BreVVOcGM4dXVUOG5kdG93MDNrRmVFL0ZnRzBObGNt?= =?utf-8?B?ekJ2ejkybGFodnRuUDExVVAzNmlmZGUyOTRzcmVZaFlaaFR4bUwrRFZLUVY4?= =?utf-8?Q?yu6M=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(1800799024)(376014)(7053199007);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Nov 2025 16:39:24.2440 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0cc0f911-ee39-4a00-1de9-08de22d33441 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9CD.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9250 Applied to drm-misc-next On 11/13/25 07:22, Falkowski, Maciej wrote: > Reviewed-by: Maciej Falkowski > > On 11/7/2025 7:11 PM, Lizhi Hou wrote: >> The mailbox interrupt register is not always cleared when a mailbox >> channel >> is created. This can leave stale interrupt states from previous >> operations. >> >> Fix this by explicitly clearing the interrupt register in the mailbox >> channel creation function. >> >> Fixes: b87f920b9344 ("accel/amdxdna: Support hardware mailbox") >> Signed-off-by: Lizhi Hou >> --- >>   drivers/accel/amdxdna/amdxdna_mailbox.c | 1 + >>   1 file changed, 1 insertion(+) >> >> diff --git a/drivers/accel/amdxdna/amdxdna_mailbox.c >> b/drivers/accel/amdxdna/amdxdna_mailbox.c >> index 24258dcc18eb..858df97cd3fb 100644 >> --- a/drivers/accel/amdxdna/amdxdna_mailbox.c >> +++ b/drivers/accel/amdxdna/amdxdna_mailbox.c >> @@ -516,6 +516,7 @@ xdna_mailbox_create_channel(struct mailbox *mb, >>       } >>         mb_chann->bad_state = false; >> +    mailbox_reg_write(mb_chann, mb_chann->iohub_int_addr, 0); >>         MB_DBG(mb_chann, "Mailbox channel created (irq: %d)", >> mb_chann->msix_irq); >>       return mb_chann;