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charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.50.2-1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Tue, 2024-03-26 at 17:28 +0000, Tudor Ambarus wrote: > When SPI transfer is being prepared, the spi-s3c64xx driver will call > clk_set_rate() to change the rate of SPI source clock (IPCLK). But IPCLK > is a gate (leaf) clock, so it must propagate the rate change up the > clock tree, so that corresponding MUX/DIV clocks can actually change > their values. Add CLK_SET_RATE_PARENT flag to corresponding clocks for > all USI instances in GS101 PERIC1: USI{0, 9, 10, 11, 12, 13}. This change > involves the following clocks: >=20 > PERIC1 USI*: >=20 > =C2=A0=C2=A0=C2=A0 Clock=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 Div range=C2=A0=C2=A0= =C2=A0 MUX Selection > =C2=A0=C2=A0=C2=A0 ------------------------------------------------------= ------------- > =C2=A0=C2=A0=C2=A0 gout_peric1_peric1_top0_ipclk_*=C2=A0=C2=A0=C2=A0 -=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 - > =C2=A0=C2=A0=C2=A0 dout_peric1_usi*_usi=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 /1..16=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 - > =C2=A0=C2=A0=C2=A0 mout_peric1_usi*_usi_user=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0 -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 {24.5 MHz, 400 MHz} >=20 > With input clock of 400 MHz this scheme provides the following IPCLK > rate range, for each USI block: >=20 > =C2=A0=C2=A0=C2=A0 PERIC1 USI*:=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 1.5 M= Hz ... 400 MHz >=20 > Accounting for internal /4 divider in SPI blocks, and because the max > SPI frequency is limited at 50 MHz, it gives us next SPI SCK rates: >=20 > =C2=A0=C2=A0=C2=A0 PERIC1 USI_SPI*:=C2=A0=C2=A0 384 KHz ... 49.9 MHz >=20 > Which shall be fine for the applications of the SPI bus. >=20 > Note that with this we allow the reparenting of the MUX_USIx clocks to > OSCCLK. Each instance of the USI IP has its own MUX_USI clock, thus the > reparenting of a MUX_USI clock corresponds to a single instance of the > USI IP. The datasheet mentions OSCCLK just in the low-power mode > context, but the downstream driver reparents too the MUX_USI clocks to > OSCCLK. Follow the downstream driver and do the same. >=20 > Fixes: 63b4bd1259d9 ("clk: samsung: gs101: add support for cmu_peric1") > Signed-off-by: Tudor Ambarus Acked-by: Andr=C3=A9 Draszik