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Wed, 26 Aug 2026 10:25:35 -0700 (PDT) X-Received: by 2002:a17:90b:51d2:b0:381:6c5:3f63 with SMTP id 98e67ed59e1d1-3966d21833dmr18520582a91.6.1787765135326; Wed, 26 Aug 2026 10:25:35 -0700 (PDT) Received: from [192.168.0.6] ([49.204.111.175]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-39668a57396sm5359403a91.13.2026.08.26.10.25.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 26 Aug 2026 10:25:34 -0700 (PDT) Message-ID: Date: Wed, 26 Aug 2026 22:55:29 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/2] i2c: qcom-geni: add I2C frequency table for 32 MHz firmware-based SEs To: Kathiravan Thirumoorthy , Mukesh Kumar Savaliya , Viken Dadhaniya , Andi Shyti , Manikanta Mylavarapu , Bjorn Andersson , Konrad Dybcio Cc: Mukesh Kumar Savaliya , linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260812-ipq5424_i2c_scl_updates-v2-0-e09cd39d01d7@oss.qualcomm.com> <20260812-ipq5424_i2c_scl_updates-v2-2-e09cd39d01d7@oss.qualcomm.com> <8d747275-fe32-4fb4-9c57-ff9bfe13ad1f@oss.qualcomm.com> Content-Language: en-US From: Praveen Talari In-Reply-To: <8d747275-fe32-4fb4-9c57-ff9bfe13ad1f@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: Wtb8k7dzXRA7MsuSkdRg-SucgxQLhaL3 X-Authority-Analysis: v=2.4 cv=VdLH+lp9 c=1 sm=1 tr=0 ts=6a8f2191 cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=MMW3c9rFXQuugNOjlkEUow==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=lhM4H5XKsiMz3D9YxmoA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 X-Proofpoint-ORIG-GUID: Wtb8k7dzXRA7MsuSkdRg-SucgxQLhaL3 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI2MDE0NSBTYWx0ZWRfX8JLfFoI2//i2 h2aIgKPBL6MQ5Lbnp3WrQIH9aTiR9/viL2SQsvc7Hm5Aalk/ibboC2bCOcHDpJsoExauO+0weo6 70tJENwpZUQ8+o6tf5zd4A49YH/fjaeB0grJOgnDPX3ZKp1iqCHcA/1JgJ4tPjO0FuTfe5KJ3Zo nz4P0jge49G4IN3wOD67uKbOhigStJruS9Jdd2S63ho/T5SjrxIiKLExk62vF2KlbaYBfZpBJb4 zJIcVLV14cftaU/2FvFza5snfRTAb0FLQZzABl+GqXOcnQeZn4FgBzQywjbwu63MaV2XzgNxxDS ITpCrZ8kqZDTmf1qULV2WTkCwVXqb/EdfutiJg+DsVH8Mr7arMMBo3Sb1ZTxTPL8x7x9LycvMWl zg659j7Hnl8QdTEzWt0V2gK1uzeMRGq2voP0VEEY5dNsVTYclVfS2R1PKO7LRooGNAaunS96qfU 8u8ITS5vcBXgSM+tagA== X-Proofpoint-Spam-Info: AW1haW4tMjYwODI2MDE0NSBTYWx0ZWRfX1m/uO3FuVaz9 /IC1/754y1NUXNraWX+KV0Z3fdcJPgiyGhE4LHAepwdGkgClgH0Y3tVZ1oqatt+e86suzSDZDxr 3ZxZHaXIl44ox+hrZFhg5Vx/aikhwlE= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-26_05,2026-08-26_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 lowpriorityscore=0 bulkscore=0 priorityscore=1501 suspectscore=0 malwarescore=0 spamscore=0 phishscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608260145 Hi Kanthiravan, On 26-08-2026 22:29, Kathiravan Thirumoorthy wrote: > > On 8/25/2026 10:50 PM, Praveen Talari wrote: >> Hi Kathiravan, >> >> On 12-08-2026 14:00, Kathiravan Thirumoorthy wrote: >>> On IPQ5424, the I2C controller can operate on both RTL-hardened SEs >>> and firmware-based SEs. As documented in commit 506bb2ab0075 >>> ("i2c: qcom-geni: Support systems with 32MHz serial engine clock"), >>> in IPQ5424 SEs use a 32 MHz source clock. >>> >>> The existing frequency table does not provide the required SCL timing >>> parameters for firmware-based SEs. Add a dedicated frequency table >>> using the SCL counter values recommended by the hardware design team >>> and select it for firmware-based SEs to achieve the target bus >>> frequencies. >>> >>> Move geni_i2c_clk_map_idx() from geni_i2c_resources_init() to >>> geni_i2c_init() to ensure SE_HW_PARAM_2 is accessed only after the >>> required clocks have been enabled. >>> >>> Signed-off-by: Kathiravan Thirumoorthy >>> >>> --- >>>   drivers/i2c/busses/i2c-qcom-geni.c | 25 ++++++++++++++++++------- >>>   include/linux/soc/qcom/geni-se.h   |  1 + >>>   2 files changed, 19 insertions(+), 7 deletions(-) >>> >>> diff --git a/drivers/i2c/busses/i2c-qcom-geni.c >>> b/drivers/i2c/busses/i2c-qcom-geni.c >>> index 00013b41a6f5..15835f10b062 100644 >>> --- a/drivers/i2c/busses/i2c-qcom-geni.c >>> +++ b/drivers/i2c/busses/i2c-qcom-geni.c >>> @@ -187,19 +187,28 @@ static const struct geni_i2c_clk_fld >>> geni_i2c_clk_map_19p2mhz[] = { >>>   }; >>>     /* source_clock = 32 MHz */ >>> -static const struct geni_i2c_clk_fld geni_i2c_clk_map_32mhz[] = { >>> +static const struct geni_i2c_clk_fld >>> geni_i2c_clk_map_32mhz_minicore[] = { >>>       { I2C_MAX_STANDARD_MODE_FREQ, 12, 9, 10, 26 }, >>>       { I2C_MAX_FAST_MODE_FREQ, 4, 3, 9, 19 }, >>>       { I2C_MAX_FAST_MODE_PLUS_FREQ, 2, 3, 5, 15 }, >>>       {} >>>   }; >>>   +static const struct geni_i2c_clk_fld >>> geni_i2c_clk_map_32mhz_fwcore[] = { >>> +    { I2C_MAX_STANDARD_MODE_FREQ, 12, 9, 10, 25 }, >>> +    { I2C_MAX_FAST_MODE_FREQ, 4, 3, 9, 18 }, >>> +    { I2C_MAX_FAST_MODE_PLUS_FREQ, 1, 6, 15, 29 }, >>> +    {} >>> +}; >>> + >>>   static int geni_i2c_clk_map_idx(struct geni_i2c_dev *gi2c) >>>   { >>>       const struct geni_i2c_clk_fld *itr; >>> +    bool is_minicore = FIELD_GET(GEN_USE_MINICORES, >>> +                     readl_relaxed(gi2c->se.base + SE_HW_PARAM_2)); >>>         if (clk_get_rate(gi2c->se.clk) == 32 * HZ_PER_MHZ) >>> -        itr = geni_i2c_clk_map_32mhz; >>> +        itr = is_minicore ? geni_i2c_clk_map_32mhz_minicore : >>> geni_i2c_clk_map_32mhz_fwcore; >> The source selection remains unchanged when using 32 MHz: >> writel_relaxed(0, gi2c->se.base + SE_GENI_CLK_SEL); > > I have to check on this. But in downstream, we didn't change this > configuration. You might not have encountered any issues because SPI and UART already request the necessary performance vote when operating at higher source clock frequencies. Without the corresponding vote from SPI and UART, we would expect failures or timing issues when switching to those higher frequencies for I2C. > >> >> However, what about the voltage requirements associated with the >> higher frequency? > > There are no such requirements in the IPQ SoC. If there are no additional voltage requirements for I2C, how are higher source clock frequencies handled for the SPI and UART GENI drivers? They also operate at source frequencies above 19.2 MHz. > >> >> Are they automatically managed by the underlying provider, or is >> additional handling needed in the driver? >> >> Reference of konrad change for CCI I2C driver for 37.5MHz with >> voltage requirement. >> >> https://lore.kernel.org/linux-arm-msm/20250904-topic-cci_updates-v1-4-d38559692703@oss.qualcomm.com/ >> >> >> >> Thanks, >> >> Praveen Talari