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[188.155.201.27]) by smtp.gmail.com with ESMTPSA id o5-20020a170906974500b006dfc781498dsm13167937ejy.37.2022.04.12.04.27.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 12 Apr 2022 04:27:44 -0700 (PDT) Message-ID: Date: Tue, 12 Apr 2022 13:27:43 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: [PATCH 3/5] ARM: dts: add dts files for bcmbca soc 47622 Content-Language: en-US To: William Zhang , Broadcom Kernel List Cc: Samyon Furman , Joel Peshkin , Florian Fainelli , Dan Beygelman , Tomer Yacoby , Anand Gore , Kursad Oney , Arnd Bergmann , Krzysztof Kozlowski , Olof Johansson , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, soc@kernel.org References: <20220411172815.20916-1-william.zhang@broadcom.com> <20220411172815.20916-4-william.zhang@broadcom.com> From: Krzysztof Kozlowski In-Reply-To: <20220411172815.20916-4-william.zhang@broadcom.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 11/04/2022 19:28, William Zhang wrote: > Add dts for ARMv7 based broadband SoC BCM47622. bcm47622.dtsi is the > SoC description dts header and bcm947622.dts is a simple dts file for > Broadcom BCM947622 Reference board that only enable the UART port. > Thank you for your patch. There is something to discuss/improve. > + */ > + > +#include > +#include > + > +/ { > + compatible = "brcm,bcm47622"; This does not match your bindings. Even if it is not used. > + #address-cells = <1>; > + #size-cells = <1>; > + > + interrupt-parent = <&gic>; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + CA7_0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a7"; > + reg = <0x0>; > + next-level-cache = <&L2_0>; > + enable-method = "psci"; > + }; > + > + CA7_1: cpu@1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a7"; > + reg = <0x1>; > + next-level-cache = <&L2_0>; > + enable-method = "psci"; > + }; > + CA7_2: cpu@2 { > + device_type = "cpu"; > + compatible = "arm,cortex-a7"; > + reg = <0x2>; > + next-level-cache = <&L2_0>; > + enable-method = "psci"; > + }; > + CA7_3: cpu@3 { > + device_type = "cpu"; > + compatible = "arm,cortex-a7"; > + reg = <0x3>; > + next-level-cache = <&L2_0>; > + enable-method = "psci"; > + }; > + L2_0: l2-cache0 { > + compatible = "cache"; > + }; > + }; > + > + timer { > + compatible = "arm,armv7-timer"; > + interrupts = , > + , > + , > + ; > + arm,cpu-registers-not-fw-configured; > + }; > + > + pmu: pmu { > + compatible = "arm,cortex-a7-pmu"; > + interrupts = , > + , > + , > + ; > + interrupt-affinity = <&CA7_0>, <&CA7_1>, > + <&CA7_2>, <&CA7_3>; > + }; > + > + clocks: clocks { > + periph_clk: periph_clk { No underscores in node names. > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <200000000>; > + }; > + uart_clk: uart_clk { > + compatible = "fixed-factor-clock"; > + #clock-cells = <0>; > + clocks = <&periph_clk>; > + clock-div = <4>; > + clock-mult = <1>; > + }; > + }; > + > + psci { > + compatible = "arm,psci-0.2"; > + method = "smc"; > + cpu_off = <1>; > + cpu_on = <2>; > + }; > + > + axi@81000000 { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0 0x81000000 0x818000>; > + > + gic: interrupt-controller@1000 { > + compatible = "arm,cortex-a7-gic"; > + #interrupt-cells = <3>; > + #address-cells = <0>; > + interrupt-controller; > + reg = <0x1000 0x1000>, > + <0x2000 0x2000>; > + }; > + }; > + > + periph-bus@ff800000 { just "bus" to be generic? Best regards, Krzysztof