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([2a01:e0a:982:cbb0:f5ba:a94c:e43a:d197]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-427a5e77493sm116329675e9.7.2024.07.16.01.45.52 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 16 Jul 2024 01:45:52 -0700 (PDT) Message-ID: Date: Tue, 16 Jul 2024 10:45:51 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: Neil Armstrong Reply-To: neil.armstrong@linaro.org Subject: Re: [PATCH v2 1/3] clk: qcom: dispcc-sm8650: Park RCG's clk source at XO during disable To: Dmitry Baryshkov Cc: Bjorn Andersson , Michael Turquette , Stephen Boyd , Konrad Dybcio , Taniya Das , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org References: <20240624-topic-sm8650-upstream-fix-dispcc-v2-0-ddaa13f3b207@linaro.org> <20240624-topic-sm8650-upstream-fix-dispcc-v2-1-ddaa13f3b207@linaro.org> <4skm6zab2xf2e4qgh4l45xzhuncmls7yfw4y77yufb7pvs2zew@rmzcgb6ozamf> Content-Language: en-US, fr Autocrypt: addr=neil.armstrong@linaro.org; keydata= xsBNBE1ZBs8BCAD78xVLsXPwV/2qQx2FaO/7mhWL0Qodw8UcQJnkrWmgTFRobtTWxuRx8WWP GTjuhvbleoQ5Cxjr+v+1ARGCH46MxFP5DwauzPekwJUD5QKZlaw/bURTLmS2id5wWi3lqVH4 BVF2WzvGyyeV1o4RTCYDnZ9VLLylJ9bneEaIs/7cjCEbipGGFlfIML3sfqnIvMAxIMZrvcl9 qPV2k+KQ7q+aXavU5W+yLNn7QtXUB530Zlk/d2ETgzQ5FLYYnUDAaRl+8JUTjc0CNOTpCeik 80TZcE6f8M76Xa6yU8VcNko94Ck7iB4vj70q76P/J7kt98hklrr85/3NU3oti3nrIHmHABEB AAHNKk5laWwgQXJtc3Ryb25nIDxuZWlsLmFybXN0cm9uZ0BsaW5hcm8ub3JnPsLAkQQTAQoA OwIbIwULCQgHAwUVCgkICwUWAgMBAAIeAQIXgBYhBInsPQWERiF0UPIoSBaat7Gkz/iuBQJk Q5wSAhkBAAoJEBaat7Gkz/iuyhMIANiD94qDtUTJRfEW6GwXmtKWwl/mvqQtaTtZID2dos04 YqBbshiJbejgVJjy+HODcNUIKBB3PSLaln4ltdsV73SBcwUNdzebfKspAQunCM22Mn6FBIxQ GizsMLcP/0FX4en9NaKGfK6ZdKK6kN1GR9YffMJd2P08EO8mHowmSRe/ExAODhAs9W7XXExw UNCY4pVJyRPpEhv373vvff60bHxc1k/FF9WaPscMt7hlkbFLUs85kHtQAmr8pV5Hy9ezsSRa GzJmiVclkPc2BY592IGBXRDQ38urXeM4nfhhvqA50b/nAEXc6FzqgXqDkEIwR66/Gbp0t3+r yQzpKRyQif3OwE0ETVkGzwEIALyKDN/OGURaHBVzwjgYq+ZtifvekdrSNl8TIDH8g1xicBYp QTbPn6bbSZbdvfeQPNCcD4/EhXZuhQXMcoJsQQQnO4vwVULmPGgtGf8PVc7dxKOeta+qUh6+ SRh3vIcAUFHDT3f/Zdspz+e2E0hPV2hiSvICLk11qO6cyJE13zeNFoeY3ggrKY+IzbFomIZY 4yG6xI99NIPEVE9lNBXBKIlewIyVlkOaYvJWSV+p5gdJXOvScNN1epm5YHmf9aE2ZjnqZGoM Mtsyw18YoX9BqMFInxqYQQ3j/HpVgTSvmo5ea5qQDDUaCsaTf8UeDcwYOtgI8iL4oHcsGtUX oUk33HEAEQEAAcLAXwQYAQIACQUCTVkGzwIbDAAKCRAWmrexpM/4rrXiB/sGbkQ6itMrAIfn M7IbRuiSZS1unlySUVYu3SD6YBYnNi3G5EpbwfBNuT3H8//rVvtOFK4OD8cRYkxXRQmTvqa3 3eDIHu/zr1HMKErm+2SD6PO9umRef8V82o2oaCLvf4WeIssFjwB0b6a12opuRP7yo3E3gTCS KmbUuLv1CtxKQF+fUV1cVaTPMyT25Od+RC1K+iOR0F54oUJvJeq7fUzbn/KdlhA8XPGzwGRy 4zcsPWvwnXgfe5tk680fEKZVwOZKIEuJC3v+/yZpQzDvGYJvbyix0lHnrCzq43WefRHI5XTT QbM0WUIBIcGmq38+OgUsMYu4NzLu7uZFAcmp6h8g Organization: Linaro In-Reply-To: <4skm6zab2xf2e4qgh4l45xzhuncmls7yfw4y77yufb7pvs2zew@rmzcgb6ozamf> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 24/06/2024 11:25, Dmitry Baryshkov wrote: > On Mon, Jun 24, 2024 at 10:05:50AM GMT, Neil Armstrong wrote: >> The RCG's clk src has to be parked at XO while disabling as per the >> HW recommendation, hence use clk_rcg2_shared_ops to achieve the same. >> >> It also changes dptx1_aux_clk_src to use the correct ops instead of >> clk_dp_ops. >> >> Fixes: 9e939f008338 ("clk: qcom: add the SM8650 Display Clock Controller driver") >> Signed-off-by: Neil Armstrong >> --- >> drivers/clk/qcom/dispcc-sm8650.c | 14 +++++++------- >> 1 file changed, 7 insertions(+), 7 deletions(-) >> >> diff --git a/drivers/clk/qcom/dispcc-sm8650.c b/drivers/clk/qcom/dispcc-sm8650.c >> index c9d2751f5cb8..360b80377ed6 100644 >> --- a/drivers/clk/qcom/dispcc-sm8650.c >> +++ b/drivers/clk/qcom/dispcc-sm8650.c >> @@ -339,7 +339,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src = { >> .parent_data = disp_cc_parent_data_0, >> .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), >> .flags = CLK_SET_RATE_PARENT, >> - .ops = &clk_rcg2_ops, >> + .ops = &clk_rcg2_shared_ops, >> }, >> }; >> >> @@ -398,7 +398,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx1_aux_clk_src = { >> .parent_data = disp_cc_parent_data_0, >> .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), >> .flags = CLK_SET_RATE_PARENT, >> - .ops = &clk_dp_ops, >> + .ops = &clk_rcg2_shared_ops, >> }, >> }; >> >> @@ -457,7 +457,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx2_aux_clk_src = { >> .parent_data = disp_cc_parent_data_0, >> .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), >> .flags = CLK_SET_RATE_PARENT, >> - .ops = &clk_rcg2_ops, >> + .ops = &clk_rcg2_shared_ops, >> }, >> }; >> >> @@ -516,7 +516,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx3_aux_clk_src = { >> .parent_data = disp_cc_parent_data_0, >> .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), >> .flags = CLK_SET_RATE_PARENT, >> - .ops = &clk_rcg2_ops, >> + .ops = &clk_rcg2_shared_ops, >> }, >> }; > > The only parent for these three clocks is the DT_BI_TCXO. Is this really > going to work as expected? Also what's the point of parking the > TCXO-sourced clocks? > Indeed will drop Thanks, Neil >> >> @@ -560,7 +560,7 @@ static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { >> .parent_data = disp_cc_parent_data_5, >> .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), >> .flags = CLK_SET_RATE_PARENT, >> - .ops = &clk_rcg2_ops, >> + .ops = &clk_rcg2_shared_ops, >> }, >> }; >> >> @@ -575,7 +575,7 @@ static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = { >> .parent_data = disp_cc_parent_data_5, >> .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), >> .flags = CLK_SET_RATE_PARENT, >> - .ops = &clk_rcg2_ops, >> + .ops = &clk_rcg2_shared_ops, >> }, >> }; >> >> @@ -647,7 +647,7 @@ static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { >> .parent_data = disp_cc_parent_data_0, >> .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), >> .flags = CLK_SET_RATE_PARENT, >> - .ops = &clk_rcg2_ops, >> + .ops = &clk_rcg2_shared_ops, >> }, >> }; >> >> >> -- >> 2.34.1 >> >