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Sun, 20 Sep 2026 04:12:11 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ThreadId: AzgOxjlYMeWB Date: Sun, 20 Sep 2026 10:11:51 +0200 From: "Arnd Bergmann" To: "Qingfang Deng" , "Paul Walmsley" , "Palmer Dabbelt" , "Albert Ou" , "Alexandre Ghiti" , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Linux-Arch Message-Id: In-Reply-To: <20260920014357.7069-2-qingfang.deng@linux.dev> References: <20260920014357.7069-1-qingfang.deng@linux.dev> <20260920014357.7069-2-qingfang.deng@linux.dev> Subject: Re: [PATCH v2 2/3] riscv: use generic MMIO accessors Content-Type: text/plain Content-Transfer-Encoding: 7bit On Sun, Sep 20, 2026, at 03:43, Qingfang Deng wrote: > RISC-V implements its raw MMIO loads and stores in inline assembly and > duplicates the generic ordered and relaxed accessors. > > Use asm-generic/mmio.h for these accessors and retain the RISC-V barrier > hooks. This preserves the ordering and MMIOWB tracking while allowing > the compiler to emit the native-width loads and stores. > > Assisted-by: Codex:gpt-6-astra > Signed-off-by: Qingfang Deng Your changelog does not explain why change it. Using inline asm is definitely the preferred way to defined the __raw_* helpers, so it would be better not to change that aspect, same as for the arm64 patch. The other simplifications look good to me, those are the bits we definitely want to have common between architectures as much as possible. Arnd