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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: EQLgFG0e98vGAzo12TlH8Gyoiqx0HExg X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTI3MDAxNyBTYWx0ZWRfXxSaFZiaq2jFC 3eF8CWzvGkz0vM3pTH8v1ig21C2RE2oQvxGaCWrnYvYEbOxuPVCjd6QA3jXqNuJsQG+RPIlVrIg SMapCWAlKZ1nM28ML6JBQcrQui6PkIFG/coHmJz1BI1ZWfR+ssg8DJVxnLYwbm6pQjX/GantC8I Cj77cWHJhOlP5os8rgy+cRSZhPpGr3qNJC1Ph/QZ148WTi99S7hUR2BmkXx13biSrFqB0pFGApq NskQMuXmGeO6GtaaWPityZGTasffhIA8WXre7rMOGnv33dC01KQkRUBpGDxOl8KPqBhckSW0KxF DDyFIdaXpTS6LojMMlc0o+K6n29D7/+HDDw7HnON92WXHZYJT+f2ENKweG3PSAtd0Kk76R5p3gp 6a7vh1QXX3RrESXS3u6axQ5GNDti7A== X-Authority-Analysis: v=2.4 cv=IeiKmGqa c=1 sm=1 tr=0 ts=68dd9ba5 cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=2kejHg7nZSoTgEpwAwsXNQ==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=EUspDBNiAAAA:8 a=DsFpUOTLdg6Fp_xZM74A:9 a=QEXdDO2ut3YA:10 a=x9snwWr2DeNwDh03kgHS:22 X-Proofpoint-ORIG-GUID: EQLgFG0e98vGAzo12TlH8Gyoiqx0HExg X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-01_06,2025-09-29_04,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 bulkscore=0 suspectscore=0 spamscore=0 adultscore=0 impostorscore=0 phishscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2509150000 definitions=main-2509270017 On 9/30/2025 12:53 PM, Dmitry Baryshkov wrote: > On Tue, Sep 30, 2025 at 11:18:15AM +0530, Akhil P Oommen wrote: >> GMU registers are always at a fixed offset from the GPU base address, >> a consistency maintained at least within a given architecture generation. >> In A8x family, the base address of the GMU has changed, but the offsets >> of the gmu registers remain largely the same. To enable reuse of the gmu > > I understand the code, but I think I'd very much prefer to see it in the > catalog file (with the note on how to calculate it). Reading resources > for two different devices sounds too strange to be nice. This way you > can keep the offsets for a6xx / a7xx untouched and just add the non-zero > offset for a8xx. It is not clear to me whether the concern is about the calculation part or the xml update part. If it is about the former,I think it is okay as we have confidence on the layout of both devices. They are not random platform devices. Also, we may have to do something similar for other gpu/gmu reg ranges too to conveniently collect a full coredump. -Akhil > >> code for A8x chipsets, update the gmu register offsets to be relative >> to the GPU's base address instead of GMU's. >> >> Signed-off-by: Akhil P Oommen >> --- >> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 44 +++- >> drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 20 +- >> drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml | 248 +++++++++++----------- >> 3 files changed, 172 insertions(+), 140 deletions(-) >