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([2a05:6e02:1041:c10:43b0:7b3b:e0d9:6992]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-3e2f6af9791sm2928315f8f.26.2025.09.05.02.44.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 05 Sep 2025 02:44:44 -0700 (PDT) Message-ID: Date: Fri, 5 Sep 2025 11:44:43 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 2/2] iio: adc: Add the NXP SAR ADC support for the s32g2/3 platforms To: David Lechner , =?UTF-8?Q?Nuno_S=C3=A1?= , jic23@kernel.org, nuno.sa@analog.com, andy@kernel.org, robh@kernel.org, conor+dt@kernel.org, krzk+dt@kernel.org Cc: linux-iio@vger.kernel.org, s32@nxp.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, chester62515@gmail.com, mbrugger@suse.com, ghennadi.procopciuc@oss.nxp.com References: <20250903102756.1748596-1-daniel.lezcano@linaro.org> <20250903102756.1748596-3-daniel.lezcano@linaro.org> <0bfce1eb-69f1-4dae-b461-234eb98ffce1@linaro.org> Content-Language: en-US From: Daniel Lezcano In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 04/09/2025 19:49, David Lechner wrote: > On 9/4/25 12:40 PM, Daniel Lezcano wrote: >> >> Hi Nuno, >> >> On 03/09/2025 13:20, Nuno Sá wrote: >>> On Wed, 2025-09-03 at 12:27 +0200, Daniel Lezcano wrote: >>>> From: Stefan-Gabriel Mirea >>>> >>>> The NXP S32G2 and S32G3 platforms integrate a successive approximation >>>> register (SAR) ADC. Two instances are available, each providing 8 >>>> multiplexed input channels with 12-bit resolution. The conversion rate >>>> is up to 1 Msps depending on the configuration and sampling window. >>>> >>>> The SAR ADC supports raw, buffer, and trigger modes. It can operate >>>> in both single-shot and continuous conversion modes, with optional >>>> hardware triggering through the cross-trigger unit (CTU) or external >>>> events. An internal prescaler allows adjusting the sampling clock, >>>> while per-channel programmable sampling times provide fine-grained >>>> trade-offs between accuracy and latency. Automatic calibration is >>>> performed at probe time to minimize offset and gain errors. >>>> >>>> The driver is derived from the BSP implementation and has been partly >>>> rewritten to comply with upstream requirements. For this reason, all >>>> contributors are listed as co-developers, while the author refers to >>>> the initial BSP driver file creator. >>>> >>>> All modes have been validated on the S32G274-RDB2 platform using an >>>> externally generated square wave captured by the ADC. Tests covered >>>> buffered streaming via IIO, trigger synchronization, and accuracy >>>> verification against a precision laboratory signal source. >>>> >>>> Co-developed-by: Alexandru-Catalin Ionita >>>> Signed-off-by: Alexandru-Catalin Ionita >>>> Co-developed-by: Ciprian Costea >>>> Signed-off-by: Ciprian Costea >>>> Co-developed-by: Radu Pirea (NXP OSS) >>>> Signed-off-by: Radu Pirea (NXP OSS) >>>> Signed-off-by: Stefan-Gabriel Mirea >>>> Co-developed-by: Daniel Lezcano >>>> Signed-off-by: Daniel Lezcano >>>> --- >> >> [ ... ] >> >>> The above needs some discussion at the very least. Have you considered the IIO >>> DMA buffer interface? It should be extendable to accommodate any particularity >>> of your usecase (or we should at least discuss it). >>> >>> With it, you also gain a userspace interface where you can actually share DMA >>> buffers in a zero copy fashion. You can also share these buffers with USB >>> gadgets. For instance, with libiio, you would be able to fetch samples from your >>> host machine (through USB) in a very fast way (zero copy between IIO and USB). >>> >>> Setting up DMA to then "having" to push it to a SW buffer and needing a syscall >>> to retrieve the data seems counter-productive. >> >> I've read a bit about the DMA engine. It is unclear how to use it and there are very few examples in the different drivers to refer to. >> >> This proposed driver supports the RAW, BUFFER and TRIGGERED. >> >> Shall I create an IIO device with the modes: >> >> indio_dev->modes = >>     INDIO_DIRECT_MODE | > > Only INDIO_DIRECT_MODE needs to be set here. > >>     INDIO_BUFFER_HARDWARE | >>     INDIO_BUFFER_TRIGGERED >> >> And then use: >> >> devm_iio_triggered_buffer_setup() > > Yes, use this and it will add INDIO_BUFFER_TRIGGERED to the flags. > >> >> and >> >> devm_iio_dmaengine_buffer_setup_with_handle > > Likewise, this will add INDIO_BUFFER_HARDWARE. > > And you likely only need to call devm_iio_dmaengine_buffer_setup() which will > save some boilerplate code. What is still unclear for me is the trigger and the dma modes. If the dma engine is supported, I should use devm_iio_dmaengine_buffer_setup_with_handle(), but will the trigger mode be supported also automatically (I don't see a clear answer in the documentation neither in the drivers) ? If not, shall I call devm_iio_triggered_buffer_setup() and devm_iio_dmaengine_buffer_setup_with_handle() ? -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog