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Thu, 31 Oct 2024 11:27:56 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Thu, 31 Oct 2024 15:27:36 +0000 From: "Jiaxun Yang" To: "Thomas Bogendoerfer" , "Gregory CLEMENT" Cc: "Aleksandar Rikalo" , "Rob Herring" , "Krzysztof Kozlowski" , "Conor Dooley" , "Vladimir Kondratiev" , "Theo Lebrun" , "Arnd Bergmann" , devicetree@vger.kernel.org, "Djordje Todorovic" , "Chao-ying Fu" , "Daniel Lezcano" , "Geert Uytterhoeven" , "Greg Ungerer" , "Hauke Mehrtens" , "Ilya Lipnitskiy" , linux-kernel@vger.kernel.org, "linux-mips@vger.kernel.org" , "Marc Zyngier" , "paulburton@kernel.org" , "Peter Zijlstra" , "Serge Semin" , "Tiezhu Yang" Message-Id: In-Reply-To: References: <20241028175935.51250-1-arikalo@gmail.com> <20241028175935.51250-11-arikalo@gmail.com> <29d7688e-5fac-4821-8764-bdc760112370@app.fastmail.com> <378f8b70-12d9-4ec3-a1e5-35bd992bfc90@app.fastmail.com> <87jzdoadve.fsf@BLaptop.bootlin.com> Subject: Re: [PATCH v8 10/13] dt-bindings: mips: cpu: Add property for broken HCI information Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable =E5=9C=A82024=E5=B9=B410=E6=9C=8831=E6=97=A5=E5=8D=81=E6=9C=88 =E4=B8=8B= =E5=8D=882:42=EF=BC=8CThomas Bogendoerfer=E5=86=99=E9=81=93=EF=BC=9A > On Thu, Oct 31, 2024 at 09:13:57AM +0100, Gregory CLEMENT wrote: >> Hi Jiaxun, >>=20 >> > =E5=9C=A82024=E5=B9=B410=E6=9C=8829=E6=97=A5=E5=8D=81=E6=9C=88 =E4=B8= =8B=E5=8D=884:11=EF=BC=8CJiaxun Yang=E5=86=99=E9=81=93=EF=BC=9A >> >> =E5=9C=A82024=E5=B9=B410=E6=9C=8829=E6=97=A5=E5=8D=81=E6=9C=88 =E4= =B8=8B=E5=8D=8812:21=EF=BC=8CAleksandar Rikalo=E5=86=99=E9=81=93=EF=BC=9A >> >> [...] >> >>> >> >>>> Is this property applicable for all MIPS vendors? There is no ve= ndor >> >>>> prefix here, so this is generic for this architecture, right? >> >> >> >> I'd say the best vendor prefix is mti in this case. >> >> >> >> CM3 IP block is supplied by MIPS Technology, it is not a part of M= IPS >> >> architecture spec. >> > >> > I just tried to revise this problem and I think a better approach w= ould >> > be picking my CM binding [1] patch and add this as a property to CM= binding. >> > >> > You don't need to pick rest of that series, this binding alone is s= ufficient, >> > and it's already being reviewed. >> > >> > Thanks >> > [1]: >> > https://lore.kernel.org/all/20240612-cm_probe-v2-5-a5b55440563c@fly= goat.com/ >>=20 >> I had a look at your series and it seems that all the issues raised w= ere >> solved, so why wasn't it merged? > > https://lore.kernel.org/all/2xkut5pyzk4b4ugl4ku72y4rfqrfsoxj4aww2jwlgk= c3lmd464@zwf773fr7fpq/ Yes this is still pending. My FPGA boards are constantly breaking down so I=E2=80=99m on radio sile= nce recently. Sorry for the confusion. Thanks > > so it's still unclear to me, whether there is something to fix or not. > > Thomas. > > --=20 > Crap can work. Given enough thrust pigs will fly, but it's not necessa= rily a > good idea. [ RFC1925, 2= .3 ] --=20 - Jiaxun