RE: [PATCH v1 3/3] mtd: spi-nor: macronix: Add 1-4-4 DTR read support for MX66L1G45G

[<Takahiro.Kuwano@infineon.com>]

> The MX66L1G45G supports the 1-4-4 DTR read mode. This flash uses 6
> dummy cycles by default in 1-4-4 DTR mode.
> 
> For 1S-4D-4D, its support bit is located in the 21st DWORD of the
> BFPT table, while the dummy cycles are described in the 23rd DWORD.
> Unfortunately, the BFPT of this flash model only provides 16 DWORDs,
> and the kernel's SFDP parser does not derive any
> SNOR_HWCAPS_READ_1_4_4_DTR capability from the BFPT table.
> 
> Since this information is expected to be in the BFPT, add a post_bfpt
> fixup which declares the 1-4-4 DTR read capability with the default 6
> dummy cycles and the 3-byte address opcode (0xED).
> 
> The SFDP of this part provides a 4BAIT table, which also advertises
> the 4-byte 1-4-4 DTR opcode (0xEE). As the capability is now set
> before the 4BAIT table is parsed, the 4BAIT parser keeps it and
> converts the opcode to its 4-byte variant, like it does for the other
> read commands.
> 
> Add a dedicated fixup for the part (SNOR_ID 0xc2, 0x20, 0x1b) that
> keeps the existing QPP 4-byte post-SFDP fixup and additionally
> advertises the 1-4-4 DTR read capability in post_bfpt.
> 
> Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
> ---

Reviewed-by: Takahiro Kuwano <takahiro.kuwano@infineon.com>