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Thu, 4 Sep 2025 03:28:57 -0500 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Thu, 4 Sep 2025 03:28:56 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Thu, 4 Sep 2025 03:28:56 -0500 Received: from [172.24.233.62] (devarsh-precision-tower-3620.dhcp.ti.com [172.24.233.62]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 5848SoWi2680491; Thu, 4 Sep 2025 03:28:50 -0500 Message-ID: Date: Thu, 4 Sep 2025 13:58:49 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] dt-bindings: drm/bridge: MHDP8546 bridge binding changes for DSC To: Rob Herring , Harikrishna Shenoy CC: , , , , , , , , , , , , , , , , , , , References: <20250903111357.2605199-1-h-shenoy@ti.com> <20250903220312.GA2903503-robh@kernel.org> Content-Language: en-US From: Devarsh Thakkar In-Reply-To: <20250903220312.GA2903503-robh@kernel.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Hi Hari, On 04/09/25 03:33, Rob Herring wrote: > On Wed, Sep 03, 2025 at 04:43:57PM +0530, Harikrishna Shenoy wrote: >> From: Swapnil Jakhade >> >> Add binding changes for DSC(Display Stream Compression) in the MHDP8546 >> DPI/DP bridge. >> >> Signed-off-by: Swapnil Jakhade >> Signed-off-by: Harikrishna Shenoy >> --- >> .../bindings/display/bridge/cdns,mhdp8546.yaml | 11 +++++++---- >> 1 file changed, 7 insertions(+), 4 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml >> index c2b369456e4e..6e749c002669 100644 >> --- a/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml >> +++ b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml >> @@ -27,6 +27,8 @@ properties: >> Register block for DSS_EDP0_INTG_CFG_VP registers in case of TI J7 SoCs. >> - description: >> Register block of mhdptx sapb registers. >> + - description: >> + Register block for mhdptx DSC encoder registers. >> >> reg-names: >> minItems: 1 >> @@ -34,6 +36,7 @@ properties: >> - const: mhdptx >> - const: j721e-intg >> - const: mhdptx-sapb >> + - const: mhdptx-dsc > > 'mhdptx' is redundant. Don't continue that pattern. Just 'dsc'. > >> >> clocks: >> maxItems: 1 >> @@ -100,18 +103,18 @@ allOf: >> properties: >> reg: >> minItems: 2 >> - maxItems: 3 >> + maxItems: 4 >> reg-names: >> minItems: 2 >> - maxItems: 3 >> + maxItems: 4 >> else: >> properties: >> reg: >> minItems: 1 >> - maxItems: 2 >> + maxItems: 3 >> reg-names: >> minItems: 1 >> - maxItems: 2 >> + maxItems: 3 > > Have you tested this works? While it might work for TI with the > j721e-intg registers in the middle, it won't work for platforms without > them. You're going to have to have 2 lists of reg-names. > Yes, as discussed offline you probably need an if else for reg blocks too here i.e. one for generic cadence compatible which would have cadence specific blocks common for all SoCs and other for j721e specific compatible which would have j721e specific reg blocks. Regards Devarsh > Rob >