From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Samuel Holland <samuel.holland@sifive.com>,
Will Deacon <will@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Eric Lin <eric.lin@sifive.com>, Conor Dooley <conor@kernel.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Paul Walmsley <paul.walmsley@sifive.com>,
linux-riscv@lists.infradead.org, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v1 1/6] dt-bindings: cache: Document the sifive,perfmon-counters property
Date: Sat, 17 Feb 2024 10:00:41 +0100 [thread overview]
Message-ID: <eeb2331d-10e6-4902-91ba-85896a8f0ee1@linaro.org> (raw)
In-Reply-To: <20240216000837.1868917-2-samuel.holland@sifive.com>
On 16/02/2024 01:08, Samuel Holland wrote:
> The SiFive Composable Cache controller contains an optional PMU with a
> configurable number of event counters. Document a property which
Configurable in what context? By chip designers or by OS? Why this
cannot be deduced from the compatible?
> describes the number of available counters.
>
> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
> ---
>
> Documentation/devicetree/bindings/cache/sifive,ccache0.yaml | 5 +++++
> 1 file changed, 5 insertions(+)
>
Best regards,
Krzysztof
next prev parent reply other threads:[~2024-02-17 9:00 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-16 0:08 [PATCH v1 0/6] SiFive cache controller PMU drivers Samuel Holland
2024-02-16 0:08 ` [PATCH v1 1/6] dt-bindings: cache: Document the sifive,perfmon-counters property Samuel Holland
2024-02-17 9:00 ` Krzysztof Kozlowski [this message]
2024-02-18 15:29 ` Samuel Holland
2024-02-18 18:35 ` Krzysztof Kozlowski
2024-02-22 19:36 ` Rob Herring
2024-04-09 15:03 ` Conor Dooley
2024-02-16 0:08 ` [PATCH v1 2/6] drivers/perf: Add SiFive Composable Cache PMU driver Samuel Holland
2024-02-19 11:29 ` Jonathan Cameron
2024-04-11 11:05 ` Robin Murphy
2024-02-16 0:08 ` [PATCH v1 3/6] dt-bindings: cache: Add SiFive Extensible Cache controller Samuel Holland
2024-02-17 9:09 ` Krzysztof Kozlowski
2024-02-18 15:50 ` Samuel Holland
2024-02-16 0:08 ` [PATCH v1 4/6] drivers/perf: Add SiFive Extensible Cache PMU driver Samuel Holland
2024-02-19 11:40 ` Jonathan Cameron
2024-02-16 0:08 ` [PATCH v1 5/6] dt-bindings: cache: Add SiFive Private L2 Cache controller Samuel Holland
2024-02-17 9:12 ` Krzysztof Kozlowski
2024-02-18 15:33 ` Samuel Holland
2024-02-16 0:08 ` [PATCH v1 6/6] drivers/perf: Add SiFive Private L2 Cache PMU driver Samuel Holland
2024-02-16 10:05 ` [PATCH v1 0/6] SiFive cache controller PMU drivers Conor Dooley
2024-04-09 15:01 ` Conor Dooley
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