From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1380E369D5D for ; Sat, 25 Jul 2026 09:33:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784972001; cv=none; b=JKI+gcRbKsGAX7DBfYFRzMNx86A3Kk2ACf4Wqw4y4bklpw0CCgrNLoeBGL9XjFBp3raD1cGIyCLRWFNpRv3AbWIEV+tVUNaORV9Y1yJUTNVCXojN415cVQfz+V4hxiPvLx77nIkCrxryJjq1y5SJkg04sv+7u9GGh/zf3GcpQIc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784972001; c=relaxed/simple; bh=sG+04XE8Gj4G3dcTHfJWO66H8jWE4iHFaBpJ1GN4+aQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Yf4jzF7lHTUycT3Z8m6t6gYJosjnkpkC5HglQZMwSV3X1HXb49pd1d0VajCmk2LKhcRq/6DqZKjn/uW6aBQ79Z/hPVYrNHd7jyAOje/CTdVswSoEnmXhJ+KAIUGDQPmJTa6rz94m7fAXae+ExHqELdEvC2od+HEE9RFRx/8j24A= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=lBL6pwMM; arc=none smtp.client-ip=198.175.65.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="lBL6pwMM" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1784972000; x=1816508000; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=sG+04XE8Gj4G3dcTHfJWO66H8jWE4iHFaBpJ1GN4+aQ=; b=lBL6pwMMotjWomAk8o8ImDEI9OeQwe2glpw9hRkAUbZdxOHu0ASK2WJ6 +0nJo0o1EU4K2fcVOMJInlCdI+fJq13o9Uc8FkmKeYrlhmAOEUg5DvqRa I+RR4q6QyfBPncyK8kCKHAqGfyVgkBiYI7CIICm4fWPM0ZddZ9N3gFfZR 9tQWgHL8e7Ov0PXvxsT+z1vIUpVTZ435O5mnhDjzD1+O9dcrHafPMswrR pIos1C22ll6FtCVUQqyz30mTolmmDq3NBatY01pn7OwVREj5R7BilgIrz BR12KpOb6YbtrQzijT/FMe5Xl1Tg5wLv0o34utZkzFXDjc470qIh0E7W2 Q==; X-CSE-ConnectionGUID: 069FvyqQTdS49MElsnVEeQ== X-CSE-MsgGUID: h9SPKgEpT7SY3+o2cMa+sA== X-IronPort-AV: E=McAfee;i="6800,10657,11855"; a="85565426" X-IronPort-AV: E=Sophos;i="6.25,184,1779174000"; d="scan'208";a="85565426" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jul 2026 02:33:20 -0700 X-CSE-ConnectionGUID: XF9YeJcZSAS4Ok8CB2hXDQ== X-CSE-MsgGUID: a8dxj+7bQEK43IO5Jes8tQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,184,1779174000"; d="scan'208";a="258372073" Received: from chenyu-dev.sh.intel.com ([10.239.62.107]) by orviesa008.jf.intel.com with ESMTP; 25 Jul 2026 02:33:17 -0700 From: Chen Yu To: tony.luck@intel.com, reinette.chatre@intel.com Cc: tglx@kernel.org, bp@alien8.de, mingo@redhat.com, dave.hansen@linux.intel.com, hpa@zytor.com, fenghuay@nvidia.com, babu.moger@amd.com, chen.yu@linux.dev, x86@kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 7/9] fs/resctrl: Do not invoke smp_processor_id() in preemptible context Date: Sat, 25 Jul 2026 17:23:33 +0800 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Tony Luck LLC occupancy can be read on any CPU when the counter is accessed via MMIO, so such an event is read from task context on whatever CPU the caller happens to be running on rather than being bounced to a CPU in the monitoring domain. mon_evt::any_cpu marks these CPU-agnostic events. __l3_mon_event_count() calls smp_processor_id() to find the CPU to read from. For an any_cpu event that lookup is unsafe: the code runs in preemptible task context, so smp_processor_id() emits a debug warning. Skip the current-CPU lookup when an event's any_cpu flag is set, events with this flag do not require execution on a specific CPU. For legacy MSR-based access, update rmid_read::err if the reading of the event was dispatched to a wrong CPU, according to the change at: https://lore.kernel.org/lkml/6b3c66a49788828bd8c04a6911bd74c91ccd56f3.1782857711.git.reinette.chatre@intel.com/ Signed-off-by: Tony Luck Signed-off-by: Chen Yu Tested-by: Hongyu Ning --- v5->v6: Drop "in a follow-up patch" from the changelog. (Reinette Chatre) Set rmid_read::err when an MSR based read is dispatched to a CPU outside the monitoring domain, to align with the conflicting change at https://lore.kernel.org/lkml/6b3c66a49788828bd8c04a6911bd74c91ccd56f3.1782857711.git.reinette.chatre@intel.com/ (Reinette Chatre) --- fs/resctrl/monitor.c | 44 ++++++++++++++++++++++++++++++++++---------- 1 file changed, 34 insertions(+), 10 deletions(-) diff --git a/fs/resctrl/monitor.c b/fs/resctrl/monitor.c index a932a1fea818..c08d2f90d721 100644 --- a/fs/resctrl/monitor.c +++ b/fs/resctrl/monitor.c @@ -422,9 +422,37 @@ static void mbm_cntr_free(struct rdt_l3_mon_domain *d, int cntr_id) memset(&d->cntr_cfg[cntr_id], 0, sizeof(*d->cntr_cfg)); } +/** + * cpu_on_correct_domain() - Check if current CPU is in the correct + * domain for the event. + * @rr: The rmid_read structure containing event and domain information. + * + * Context: Preemptible process context when @rr->evt->any_cpu is set. + * Non-migratable process context (via smp_call_on_cpu()) or + * non-preemptible context (via smp_call_function_any()) when + * the event must be read on a specific CPU. + * Return: true if the current CPU can read this event, false otherwise. + */ +static bool cpu_on_correct_domain(struct rmid_read *rr) +{ + int cpu; + + /* Any CPU is OK for this event */ + if (rr->evt->any_cpu) + return true; + + cpu = smp_processor_id(); + + /* Single domain. Must be on a CPU in that domain. */ + if (rr->hdr) + return cpumask_test_cpu(cpu, &rr->hdr->cpu_mask); + + /* Summing domains that share a cache, must be on a CPU for that cache. */ + return cpumask_test_cpu(cpu, &rr->ci->shared_cpu_map); +} + static int __l3_mon_event_count(struct rdtgroup *rdtgrp, struct rmid_read *rr) { - int cpu = smp_processor_id(); u32 closid = rdtgrp->closid; u32 rmid = rdtgrp->mon.rmid; struct rdt_l3_mon_domain *d; @@ -457,9 +485,6 @@ static int __l3_mon_event_count(struct rdtgroup *rdtgrp, struct rmid_read *rr) return 0; } - /* Reading a single domain, must be on a CPU in that domain. */ - if (!cpumask_test_cpu(cpu, &d->hdr.cpu_mask)) - return -EINVAL; if (rr->is_mbm_cntr) rr->err = resctrl_arch_cntr_read(rr->r, d, closid, rmid, cntr_id, rr->evt->evtid, &tval); @@ -477,7 +502,6 @@ static int __l3_mon_event_count(struct rdtgroup *rdtgrp, struct rmid_read *rr) static int __l3_mon_event_count_sum(struct rdtgroup *rdtgrp, struct rmid_read *rr) { - int cpu = smp_processor_id(); u32 closid = rdtgrp->closid; u32 rmid = rdtgrp->mon.rmid; struct rdt_l3_mon_domain *d; @@ -495,10 +519,6 @@ static int __l3_mon_event_count_sum(struct rdtgroup *rdtgrp, struct rmid_read *r return -EINVAL; } - /* Summing domains that share a cache, must be on a CPU for that cache. */ - if (!cpumask_test_cpu(cpu, &rr->ci->shared_cpu_map)) - return -EINVAL; - /* * Legacy files must report the sum of an event across all * domains that share the same L3 cache instance. @@ -529,7 +549,11 @@ static int __mon_event_count(struct rdtgroup *rdtgrp, struct rmid_read *rr) { switch (rr->r->rid) { case RDT_RESOURCE_L3: - WARN_ON_ONCE(rr->evt->any_cpu); + if (!cpu_on_correct_domain(rr)) { + rr->err = -EIO; + return -EINVAL; + } + if (rr->hdr) return __l3_mon_event_count(rdtgrp, rr); else -- 2.25.1