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ORIGINATING; auth=pass smtp.auth=pza@pengutronix.de smtp.mailfrom=p.zabel@pengutronix.de ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=pengutronix.de; s=20260414; t=1792660971; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=4wmcDPWEKLBzrIxX+Ibo0uWDTHVsLEg1YsLnub8SYKk=; b=DFxMgagx3VDAvleH0DdLcAiesq/JJe8gxfeFnhPYLtAHu7tEyyyvFSiYgWmnzlr/hoWOym dG6BxplaEByLQzBLjoANNbWbT2NxTt1QkviLMgt644ty+rWXKVSoloqUTihCw9GQgko1Sf uHUFmuatBvcFLc6Kbhx+mnvQAjQIXip+24zGQeW2L7N7O+W30ttoHwAyeINbLyxfDYkVOm F0e40HVUpWom7ZM9i3oh1ukfmACay2y7dbL9xrtJauc50kTjv0/vuOC26ObD773IwApaCt NcCb75Db5ojo4VD2A0e8T1wKXazqQAQTNw3HyBw/uHpPIZxeSeO1tciYK9HcLQ== Message-ID: Subject: Re: [PATCH 14/18] riscv: dts: zhihe: add A210 UARTs From: Philipp Zabel To: gaohan@iscas.ac.cn, Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Zhiguo Zhu , Stephen Boyd , Brian Masney , Jerome Brunet , Linus Walleij , Bartosz Golaszewski , Thomas Gleixner , Radu Rendec , Samuel Holland , Daniel Lezcano , Anup Patel , Icenowy Zheng , Drew Fustini Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, Paul Walmsley Date: Thu, 22 Oct 2026 11:22:51 +0200 In-Reply-To: <20261022-a210-init-v1-14-5e438f972d24@iscas.ac.cn> References: <20261022-a210-init-v1-0-5e438f972d24@iscas.ac.cn> <20261022-a210-init-v1-14-5e438f972d24@iscas.ac.cn> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.56.2-0+deb13u1 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 On Do, 2026-10-22 at 03:53 +0800, Han Gao via B4 Relay wrote: > From: Zhiguo Zhu >=20 > Add the ten A210 UARTs with their clocks, resets and interrupts, using > the snps,dw-apb-uart compatible. >=20 > Signed-off-by: Zhiguo Zhu > Co-developed-by: Han Gao > Signed-off-by: Han Gao > --- > arch/riscv/boot/dts/zhihe/a210.dtsi | 150 ++++++++++++++++++++++++++++++= ++++++ > 1 file changed, 150 insertions(+) >=20 > diff --git a/arch/riscv/boot/dts/zhihe/a210.dtsi b/arch/riscv/boot/dts/zh= ihe/a210.dtsi > index bbad51a3edb0..a07b67d10633 100644 > --- a/arch/riscv/boot/dts/zhihe/a210.dtsi > +++ b/arch/riscv/boot/dts/zhihe/a210.dtsi > @@ -405,6 +405,66 @@ rst_peri1: reset-controller@2010400 { > #reset-cells =3D <1>; > }; > =20 > + uart0: serial@2014000 { > + compatible =3D "snps,dw-apb-uart"; Prepend a vendor compatible if you need two resets, similar to "starfive,jh7100-uart"? > + reg =3D <0x0 0x02014000 0x0 0x400>; > + clocks =3D <&clk_peri PERI1_UART0_SCLK_EN>, > + <&clk_peri PERI1_UART0_PCLK_EN>; > + clock-names =3D "baudclk", "apb_pclk"; > + interrupt-parent =3D <&intc>; > + interrupts =3D <321 IRQ_TYPE_LEVEL_HIGH>; > + reg-io-width =3D <4>; > + reg-shift =3D <2>; > + resets =3D <&rst_peri1 PERI1_UART0_PRST>; This looks to me like it should be resets =3D <&rst_peri1 PERI1_UART0_PRST>, <&rst_peri1 PERI1_UART0_S_RST>; instead. regards Philipp