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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: GW5ihL3g+b4tl9a3rfcNoVCdnshoeQ73xkE3Xib9pfzrVd5SxvgstaL1QGYFiivY5t7Q2xqGIYl67QCv1E753icSksTNzLqArb/2AUYTJGjAADNL/ZE801SmzugstJyWaO8APlEbEYwPmCLKOT5Ya1b31rf3AGghkM4vXZ09R+QoF7c8LOuBE7NVCBeQ0XzFQsDqWIBI05JhyIKIGw5AA3XGCiYjwCP5wHoaS+0vlb9+1hVtwIS9llKWPhfrvNkN/rMqCAkad+8TUnaeWylrbikcWSwiBsrxg4Wa3JBV2FnG7Uxx+C+aFp8v/aR2JmK9Iwo3EW1G1AIfNvBnJonpRx63+TTR6THYIAeGUB/VcLW3B5Ix2ocRATNnJWRESmHdOvZFPCyEr5bVNV17LYnlwBP2GOtp3N1ITBW0/rpGj+XaQOiWphJlN6qRNtwphhV2 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Sep 2026 20:09:18.8125 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 862ddb7a-e6e6-4e7a-f60a-08df0de510b2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003F67.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB999319 Hello Andrea, On 9/8/2026 1:53 PM, Andrea Righi wrote: > NVIDIA Olympus implements spatial SMT with symmetric steady-state PE > capacity but two different resource modes. One-Thread Active mode gives > one PE the full core, while waking the other PE restores Two-Thread > Active mode and partitions decode, issue, cache, TLB, and vector > resources. Returning to full-resource mode requires the sibling to > remain in WFI for 10 Ki cycles. > > Measurements show that pinned workloads perform equally on either PE, > but freely migratable workloads lose substantial throughput when they > alternate between PE identities. Consistently selecting PE0 keeps PE1 > idle, avoids repeated SMT repartitioning, and restores > one-thread-per-core performance. > > Describe this scheduling preference with SD_ASYM_PACKING and give PE0, > identified by MPIDR_EL1.Aff0, the higher arch_asym_cpu_priority(). This > is independent of SD_ASYM_CPUCAPACITY: SMT siblings retain equal > capacity, while physical cores with different maximum frequencies are > handled by a higher scheduling domain. > > Firmware currently provides no interface for describing the preferred > SMT sibling. Detect Olympus by MIDR until such an interface is > available. > > Signed-off-by: Andrea Righi Feel free to include: Reviewed-by: K Prateek Nayak Tested-by: K Prateek Nayak Just one nit below ... > +/* > + * Switching the active PE on an NVIDIA Olympus SMT core can keep the core in > + * two-thread active mode, with resources partitioned between the PEs. > + * > + * Prefer PE0 so PE1 can remain idle and the core can stay in full-resource > + * mode. Firmware does not currently describe this preference, so detect > + * Olympus by MIDR until a firmware interface is available. > + */ > +static bool olympus_prefer_pe0 __ro_after_init; nit. What is the purpose of "olympus_prefer_pe0"? > + > +#ifdef CONFIG_SCHED_SMT > +static int arm64_smt_flags(void) > +{ > + int flags = cpu_smt_flags(); > + > + if (olympus_prefer_pe0) > + flags |= SD_ASYM_PACKING; If this flag function is being used, olympus_prefer_pe0 is always true, and the scheduler will never call into arch_asym_cpu_priority() without SD_ASYM_PACKING being set so olympus_prefer_pe0 is always true there too. Seems redundant unless you were planning to do set_sched_topology() unconditionally for whole of arm64. > + > + return flags; > +} -- Thanks and Regards, Prateek