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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2e8422b8d9asm65203255ad.62.2026.10.14.01.33.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 14 Oct 2026 01:33:48 -0700 (PDT) Message-ID: Date: Wed, 14 Oct 2026 16:33:43 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] arm64: dts: qcom: shikra: Switch CPU ETMs to MMIO-based probing To: Konrad Dybcio , Bjorn Andersson , Konrad Dybcio , Abel Vesa , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jie Gan References: <20260922-fix-etm-probe-issue-on-shikra-v1-1-56d25e9bbe17@oss.qualcomm.com> <3fe1ac52-f69a-4288-88b6-edb5717dd315@oss.qualcomm.com> <2a6b9567-e07e-40ae-a214-2a4d6bcb29d1@oss.qualcomm.com> <1a8f0ef0-303d-4173-bfc2-ec8dd952f367@oss.qualcomm.com> Content-Language: en-US From: Jie Gan In-Reply-To: <1a8f0ef0-303d-4173-bfc2-ec8dd952f367@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Info: AW1haW4tMjYxMDE0MDAzMyBTYWx0ZWRfXx72JufBocgQ4 OkuZAbI3U4N4fuFvwjr5FUbJxLMlximIgxiq9H1VgGC/p/Cp8xlPnn93Jj00bCk455L8SPIDiJC PZb5t2kCCDdHF0ah1uZ74f7RT56ZE6M= X-Proofpoint-ORIG-GUID: 4Lpx30vn5oAVYyRbKF6djIOZYYDRcLtt X-Authority-Analysis: v=2.4 cv=aeb0Dhot c=1 sm=1 tr=0 ts=6acf3e6e cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=ESQR0jG560GBcKQeWBMA:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDE0MDAzMyBTYWx0ZWRfXw0fAsI83AEwy 1BOZzbOJUZGjdIKUgbmhK0Og7JLmiP5ZSPB8rk+RfBZnjbMpsfGdXlxBt3dbLsZsXLTxawln9VB pj0gwmwN3QY/FoDWUUJFdAP17F2YAAgYEc3Uq5J5UsQkc3SQOCkvyAIFWe1o9zz6InCpTnEUEGn a+ZTgew1WBjSbh/K6KOh8bUnJbZ91SeBm3l+8xIxZ7ykQiLKRn6GsR5vwy9B4vbPcBj2J4vFQyd sByatb52AXP1s2tf/pvN96ukeECMhqFppSLtwPTtIMFL1x3V0bLwVoYho2HrLzXxQ44U9EEEKn/ bsG2XHvBO3hIvkO5hw8CchqhwqjZn/QzRFag+QpP6i6GzYhqYnnngbwZA/D7M2jifyaGq0xY3Xi o8ZoFeUCgGtqCtJ4u/i9LcS4ehll6eZSAYIh9Pizw3McP72AcB0xIYkglawDz82i68MU8tqCMKQ ii9IumYZvmovKWDE5/A== X-Proofpoint-GUID: 4Lpx30vn5oAVYyRbKF6djIOZYYDRcLtt X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-13_01,2026-10-09_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 bulkscore=0 lowpriorityscore=0 impostorscore=0 suspectscore=0 spamscore=0 priorityscore=1501 malwarescore=0 clxscore=1015 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610080000 definitions=main-2610140033 On 10/14/2026 4:31 PM, Konrad Dybcio wrote: > On 10/14/26 10:19 AM, Jie Gan wrote: >> >> >> On 10/13/2026 8:38 PM, Konrad Dybcio wrote: >>> On 9/22/26 5:09 AM, Jie Gan wrote: >>>> The etm0-etm3 nodes are declared with "arm,coresight-etm4x-sysreg" >>>> but do not implement self-hosted system-register trace access on >>>> this SoC: ID_AA64DFR0_EL1.TraceVer reads as 0 on the affected CPUs, >>>> so etm4_init_sysreg_access() correctly reports the access mechanism >>>> as unavailable and the ETMv4 driver fails to probe with -EINVAL. >>>> >>>> The CPU ETMs have a memory-mapped aperture, so switch each node to >>>> the standard "arm,coresight-etm4x", "arm,primecell" compatible with >>>> its MMIO reg range. >>>> >>>> Fixes: eed738c6dd0c ("arm64: dts: qcom: shikra: Add coresight nodes") >>>> Signed-off-by: Jie Gan >>>> --- >>> >>> Do we still need qcom,skip-power-up on new SoCs *with* MMIO access? >>> >> >> Yes, we need qcom,skip-power-up for all ETM device with or w/o MMIO access. >> >>> GPT has concerns regarding whether we need to add >>> arm,coresight-loses-context-with-cpu> >> >> This logic to be handled by HYP on Shikra SoC, so I didnt enable it in kernel. > > https://lore.kernel.org/linux-arm-msm/20261005-shikra-el2-v3-0-618f7343695c@oss.qualcomm.com/ > > We're going to, in parallel, ship Shikra without the Qualcomm > hypervisor so please keep that in mind. Should the submitters of the > non-Gunyah overlay add these properties there as they respin? Does > that concern all Coresight components? Making sense. I will add the property. Thanks, Jie > > Konrad