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smtp.subspace.kernel.org; dkim=pass header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b=FDbY6ecL; arc=none smtp.remote-ip=100.103.45.18 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9AF12606BEB3; Thu, 5 Nov 2026 15:54:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key, unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b=FDbY6ecL Received: by smtp.kernel.org (Postfix) with ESMTPSA id 215C11F00919; Thu, 5 Nov 2026 15:54:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1793894056; bh=Qx04Fn5WCCUloxDGXEqPfWbEyZHIMrkGFVFAAcnvj1E=; h=Date:Subject:To:Cc:References:From:In-Reply-To; b=FDbY6ecLi6mWL7FJRAbLrcM5KnAZ/8AO2YmGzmgM9tRu3xfgC1hqenhOxLYPMppzU RBtd8et/HLr1iC1EljSG1gqA6qqAffYRAQWOpO5LhWqPrhWDOfo1hv5JtBorkS3oiW IK8J9HmOVZ78eiUwoXzVMdTCufp3o/v0Ck/UHDWlEyFVr4auBLcoVgAAWEeHwa2PII nnBY0oMzO/kzNov6xN/g91eNuK6SWRU1lEOSZJarBuYx4np3FunuLl4Ay5BAG5tXj/ PgdoITEzcLRV8qGuGrtg6t7SvtTXGBDf27lSFvGGMXw4GccsDCt6xCClzErPkJyh3Z yUpm42boZzeQw== Message-ID: Date: Thu, 5 Nov 2026 15:54:11 +0000 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/2] dt-bindings: media: qcom,glymur-camss: Use CSIPHY indices for ports To: Vladimir Zapolskiy , Loic Poulain , Krzysztof Kozlowski Cc: Nihal Kumar Gupta , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue , linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Suresh Vankadara , Vikram Sharma References: <20261102-glymur_camss-v1-0-fcb619fc7319@oss.qualcomm.com> <20261102-glymur_camss-v1-1-fcb619fc7319@oss.qualcomm.com> <20261104-real-nebulous-ostrich-017e92@quoll> <72064a9a-1b2e-4c24-99e2-2cc15a8dd7f1@oss.qualcomm.com> <539842db-c672-4549-b861-4a6f3be47556@oss.qualcomm.com> <1db9bf48-01d8-44fe-8dd2-7a3c84ecc556@kernel.org> <62fba00d-831c-44cc-8d3e-083a95abfbe8@kernel.org> <4d656385-fd3b-426d-b326-b1d20ba1e2d7@linaro.org> From: Bryan O'Donoghue Content-Language: en-GB Autocrypt: addr=bod@kernel.org; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 05/11/2026 15:39, Vladimir Zapolskiy wrote: >> Today, the Glymur bindings define DT ports { 0, 1, 3 } to map to PHY >> indices { 0, 1, 4 }. One could argue that this is already an >> established convention, as it is documented in the bindings. However, >> it is somewhat confusing. >> > I believe it should be fine to have incontiguous port indices, because > there is no need to link unused phys to CAMSS on any particular board, > therefore there will be unavoidable "holes", and this can be set right > in the documentation of CSIPHY to CAMSS connection. > > -- > Best wishes, > Vladimir I mean the port numbers currently mean absolutely nothing with standalone PHYs so in that sense I agree. OTOH since the numbers mean nothing - they should probably be linear, it's just confusing to have non-linear port numbering. For legacy PHYs numbering ports after the PHYs is something we inherited and worked with. For the new scheme it serves no purpose. --- bod