From: Philippe CORNU <philippe.cornu@st.com>
To: Yannick FERTRE <yannick.fertre@st.com>,
Benjamin Gaignard <benjamin.gaignard@linaro.org>,
Vincent ABRIOU <vincent.abriou@st.com>,
"David Airlie" <airlied@linux.ie>,
"dri-devel@lists.freedesktop.org"
<dri-devel@lists.freedesktop.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Peter Rosin <peda@axentia.se>
Cc: Fabien DESSENNE <fabien.dessenne@st.com>,
Mickael REULIER <mickael.reulier@st.com>,
Gabriel FERNANDEZ <gabriel.fernandez@st.com>,
Ludovic BARRE <ludovic.barre@st.com>,
Alexandre TORGUE <alexandre.torgue@st.com>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>
Subject: Re: [PATCH] drm/stm: ltdc: add clut mode support
Date: Tue, 7 Nov 2017 15:53:21 +0000 [thread overview]
Message-ID: <ef52d53e-9a33-a2fd-c184-d76a8c092dc4@st.com> (raw)
In-Reply-To: <1509016666-18927-1-git-send-email-philippe.cornu@st.com>
+ Peter
Hi Peter,
CLUT support on STM32 has been removed thanks to your clean up patch
named "drm: stm: remove dead code and pointless local lut storage"
(https://patchwork.freedesktop.org/patch/166898/)
This below patch puts back the clut mode support using the new drm gamma
api.
May I ask you please a short review on this patch?
Many thanks,
Philippe :-)
On 10/26/2017 01:17 PM, Philippe Cornu wrote:
> Add the 8-bit clut mode support at crtc level.
> Useful for low memory footprint user interfaces but also for
> 8-bit old games (including color shifting visual effects).
> Tested with fbdev FBIOPUTCMAP & drm DRM_IOCTL_MODE_SETGAMMA
> ioctls.
>
> Signed-off-by: Philippe Cornu <philippe.cornu@st.com>
> ---
> drivers/gpu/drm/stm/ltdc.c | 30 ++++++++++++++++++++++++++++++
> 1 file changed, 30 insertions(+)
>
> diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c
> index 7be6710..d5c8a42 100644
> --- a/drivers/gpu/drm/stm/ltdc.c
> +++ b/drivers/gpu/drm/stm/ltdc.c
> @@ -174,6 +174,8 @@
>
> #define LXCFBLNR_CFBLN GENMASK(10, 0) /* Color Frame Buffer Line Number */
>
> +#define CLUT_SIZE 256
> +
> #define CONSTA_MAX 0xFF /* CONSTant Alpha MAX= 1.0 */
> #define BF1_PAXCA 0x600 /* Pixel Alpha x Constant Alpha */
> #define BF1_CA 0x400 /* Constant Alpha */
> @@ -362,6 +364,28 @@ static irqreturn_t ltdc_irq(int irq, void *arg)
> * DRM_CRTC
> */
>
> +static void ltdc_crtc_update_clut(struct drm_crtc *crtc)
> +{
> + struct ltdc_device *ldev = crtc_to_ltdc(crtc);
> + struct drm_color_lut *lut;
> + u32 val;
> + int i;
> +
> + if (!crtc || !crtc->state)
> + return;
> +
> + if (!crtc->state->color_mgmt_changed || !crtc->state->gamma_lut)
> + return;
> +
> + lut = (struct drm_color_lut *)crtc->state->gamma_lut->data;
> +
> + for (i = 0; i < CLUT_SIZE; i++, lut++) {
> + val = ((lut->red << 8) & 0xff0000) | (lut->green & 0xff00) |
> + (lut->blue >> 8) | (i << 24);
> + reg_write(ldev->regs, LTDC_L1CLUTWR, val);
> + }
> +}
> +
> static void ltdc_crtc_atomic_enable(struct drm_crtc *crtc,
> struct drm_crtc_state *old_state)
> {
> @@ -485,6 +509,8 @@ static void ltdc_crtc_atomic_flush(struct drm_crtc *crtc,
>
> DRM_DEBUG_ATOMIC("\n");
>
> + ltdc_crtc_update_clut(crtc);
> +
> /* Commit shadow registers = update planes at next vblank */
> reg_set(ldev->regs, LTDC_SRCR, SRCR_VBR);
>
> @@ -532,6 +558,7 @@ void ltdc_crtc_disable_vblank(struct drm_device *ddev, unsigned int pipe)
> .reset = drm_atomic_helper_crtc_reset,
> .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
> .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
> + .gamma_set = drm_atomic_helper_legacy_gamma_set,
> };
>
> /*
> @@ -764,6 +791,9 @@ static int ltdc_crtc_init(struct drm_device *ddev, struct drm_crtc *crtc)
>
> drm_crtc_helper_add(crtc, <dc_crtc_helper_funcs);
>
> + drm_mode_crtc_set_gamma_size(crtc, CLUT_SIZE);
> + drm_crtc_enable_color_mgmt(crtc, 0, false, CLUT_SIZE);
> +
> DRM_DEBUG_DRIVER("CRTC:%d created\n", crtc->base.id);
>
> /* Add planes. Note : the first layer is used by primary plane */
>
next prev parent reply other threads:[~2017-11-07 15:53 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-10-26 11:17 Philippe Cornu
2017-11-07 15:53 ` Philippe CORNU [this message]
2017-11-07 16:34 ` Peter Rosin
2017-11-10 16:12 ` Philippe CORNU
2017-11-12 12:31 ` Peter Rosin
2017-11-13 10:40 ` Philippe CORNU
2017-11-24 13:54 ` Philippe CORNU
2017-11-24 15:44 ` Peter Rosin
2018-01-09 11:28 ` Philippe CORNU
2018-01-09 11:56 ` Peter Rosin
2018-01-09 13:05 ` Benjamin Gaignard
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