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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: zRYf5QUSa2EevLESDNPzuee4KYrMLD77BTU5xOgluLJ45YhVuc7d9BHN9tXpZUgV1e+lblYiws71GIJ91/xZRPLGq6b+k8LQVu+Jj+JUCrYUl4eVi0MZdVXZ47+ocA5v3VUvFRzrY5aINeLhEy0pRYcmKXoIfBfH/ZmaAJ7qhBQItao7RwRESnztCKzJ1/YfmmXbmoLQK+dsMLZ04V2dP3E4Q4MrLM4+X1/64XilYZbs4Es2qSBURO6MU2E7khEeBLjvkO1S5UPfBr4KUXl7EXoRPUYjs5swxjFunwLcPGchHmbnw9dAGI6LcEOleSKBfn8zlH9S8x7Ue6rO0mAQX+Ch8hQ+SjgBoN50wBMBeERatFBwjLz7hf9Uqx/etYpBxp6ly8sLxYUB5cMv5koYb3QVVuj/EjBCmL8RquL05S45kLw4jeiZnINyG5678zMn X-OriginatorOrg: foss.st.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2026 13:43:19.9624 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2d9a1023-7d14-4715-7f73-08df3a799687 X-MS-Exchange-CrossTenant-Id: 75e027c9-20d5-47d5-b82f-77d7cd041e8f X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=75e027c9-20d5-47d5-b82f-77d7cd041e8f;Ip=[164.130.1.59];Helo=[smtpO365.st.com] X-MS-Exchange-CrossTenant-AuthSource: DB1PEPF000509FF.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM7PR10MB3671 On 10/17/26 19:52, Krzysztof Kozlowski wrote: > On Fri, Oct 16, 2026 at 05:26:04PM +0200, Patrice Chotard wrote: >> The STM32 TAMP node (compatible "st,stm32-tamp", "syscon", "simple-mfd") >> exposes its backup registers through an nvram child node described by >> nvmem/st,stm32-tamp-nvram.yaml. That requires the TAMP node to carry >> "#address-cells", "#size-cells", "ranges" and an "nvram@..." child. >> >> st,stm32-syscon.yaml uses "additionalProperties: false" and only allowed >> reg/clocks/#clock-cells, so wiring the nvram provider into the DTSI made >> "make dtbs_check" fail on every STM32MP TAMP node: >> >> tamp@5c00a000 (st,stm32-tamp): '#address-cells', '#size-cells', >> 'nvram@5c00a100', 'ranges' do not match any of the regexes: >> '^pinctrl-[0-9]+$' > > There are no children of tamp@5c00a000 in > arch/arm/boot/dts/st/stm32mp151.dtsi. How is it possible to reproduce > this warning? > > Are you using some other patches bugs as a reason of change in bindings? Hi Krzysztof yes, in this patch [1] arch/arm/boot/dts/st/stm32mp151.dtsi is updated that's why bindings need this change. See the complete series [2]. [1] https://patchwork.kernel.org/project/linux-arm-kernel/patch/20260930-upstream_tamp_nvram_dts_part-v2-2-bd73158ce46b@foss.st.com/ [2] https://patchwork.kernel.org/series/1176665/ > >> >> Allow the addressing properties and the nvram child, gated on the >> st,stm32-tamp compatible so the other syscon variants stay strict. >> "#size-cells" may be 1 or 2: the STM32MP21 soc bus uses two size cells >> (an empty "ranges" requires the node to match its parent) while the >> other STM32MP SoCs use one. >> >> Signed-off-by: Patrice Chotard >> --- >> .../bindings/arm/stm32/st,stm32-syscon.yaml | 30 ++++++++++++++++++++++ >> 1 file changed, 30 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml >> index 95d2319afe23..1aeb54867db2 100644 >> --- a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml >> +++ b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml >> @@ -39,6 +39,23 @@ properties: >> "#clock-cells": >> const: 0 >> >> + "#address-cells": >> + const: 1 >> + >> + "#size-cells": >> + enum: [1, 2] >> + >> + ranges: true > > You work on some weeks old tree. Indeed, this series need to be rebased on top of v7.4-rc1 Thanks Patrice > >> + >> +patternProperties: >> + "^nvram@[0-9a-f]+$": >> + type: object > > additionalProperties true with ref or false with a compatible, just like > every other binding. See also display/msm for some examples. > >> + description: >> + TAMP backup registers exposed as an NVMEM provider. See >> + nvmem/st,stm32-tamp-nvram.yaml. >> + required: >> + - compatible > > Best regards, > Krzysztof >