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Tue, 11 Feb 2025 00:26:09 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 51B0Q8h4029026 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 11 Feb 2025 00:26:08 GMT Received: from [10.71.110.136] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 10 Feb 2025 16:26:07 -0800 Message-ID: Date: Mon, 10 Feb 2025 16:26:06 -0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/4] drm/msm/dsi/phy: Protect PHY_CMN_CLK_CFG0 updated from driver side To: Krzysztof Kozlowski , Rob Clark , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter CC: , , , References: <20250203-drm-msm-phy-pll-cfg-reg-v2-0-862b136c5d22@linaro.org> <20250203-drm-msm-phy-pll-cfg-reg-v2-1-862b136c5d22@linaro.org> Content-Language: en-US From: Abhinav Kumar In-Reply-To: <20250203-drm-msm-phy-pll-cfg-reg-v2-1-862b136c5d22@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Ux8XyDGsldKWABFEwHyztXvO7Qac-Ged X-Proofpoint-ORIG-GUID: Ux8XyDGsldKWABFEwHyztXvO7Qac-Ged X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-10_12,2025-02-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 priorityscore=1501 clxscore=1015 suspectscore=0 mlxscore=0 lowpriorityscore=0 phishscore=0 impostorscore=0 malwarescore=0 spamscore=0 mlxlogscore=985 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502100180 On 2/3/2025 9:29 AM, Krzysztof Kozlowski wrote: > PHY_CMN_CLK_CFG0 register is updated by the PHY driver and by two > divider clocks from Common Clock Framework: > devm_clk_hw_register_divider_parent_hw(). Concurrent access by the > clocks side is protected with spinlock, however driver's side in > restoring state is not. Restoring state is called from > msm_dsi_phy_enable(), so there could be a path leading to concurrent and > conflicting updates with clock framework. > > Add missing lock usage on the PHY driver side, encapsulated in its own > function so the code will be still readable. > > Fixes: 1ef7c99d145c ("drm/msm/dsi: add support for 7nm DSI PHY/PLL") > Signed-off-by: Krzysztof Kozlowski > --- > drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 13 +++++++++++-- > 1 file changed, 11 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > index 031446c87daec0af3f81df324158311f5a80014e..c164f845653816291ad96c863257f75462ef58e7 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > @@ -372,6 +372,15 @@ static void dsi_pll_enable_pll_bias(struct dsi_pll_7nm *pll) > ndelay(250); > } > Reviewed-by: Abhinav Kumar