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X-CSE-ConnectionGUID: SsmCtVAuTeSNFAPjityaOA== X-CSE-MsgGUID: Sv5q2OacSfmlkv5M5mLinw== X-IronPort-AV: E=McAfee;i="6700,10204,11107"; a="15781745" X-IronPort-AV: E=Sophos;i="6.08,247,1712646000"; d="scan'208";a="15781745" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jun 2024 10:59:07 -0700 X-CSE-ConnectionGUID: nx+YDu7ESCGyuJgNf8L6iA== X-CSE-MsgGUID: DkyZIxT8SXaUdNhv+jeLog== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,247,1712646000"; d="scan'208";a="41586534" Received: from mgoodin-mobl2.amr.corp.intel.com (HELO [10.124.220.122]) ([10.124.220.122]) by fmviesa008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jun 2024 10:59:06 -0700 Message-ID: Date: Tue, 18 Jun 2024 10:59:06 -0700 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] perf/x86/intel/pt: Update topa_entry base len to support 52-bit physical addresses To: Marco Cavenati , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: peterz@infradead.org, mingo@redhat.com, acme@kernel.org, namhyung@kernel.org, mark.rutland@arm.com, alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, kan.liang@linux.intel.com, tglx@linutronix.de, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com References: <20240618110617.22626-1-cavenati.marco@gmail.com> From: Dave Hansen Content-Language: en-US Autocrypt: addr=dave.hansen@intel.com; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 6/18/24 04:06, Marco Cavenati wrote: > Increase topa_entry base to 40 bits to accommodate page addresses in > systems with 52-bit physical addresses. > The Base Physical Address field (base) has a length of MAXPHYADDR - 12 as > stated in Intel's SDM chapter 33.2.7.2. > The maximum MAXPHYADDR is 52 as stated in SDM 4.1.4. > Therefore, the maximum base bit length is 40. This makes it sound like it's _adding_ support for larger physical addresses. It really was a bug from day one. MAXPHYADDR has been defined to be "at most 52" for a long, long time. I think it was well before 5-level paging came on the scene and actual MAXPHYADDR=52 systems came along. It probably needs to say something more along the lines of: topa_entry->base needs to store a pfn. It obviously needs to be large enough to store the largest possible x86 pfn which is MAXPHYADDR-PAGE_SIZE (52-12). So it is 4 bits too small. This isn't the only bug in the area: > static void *pt_buffer_region(struct pt_buffer *buf) > { > return phys_to_virt(TOPA_ENTRY(buf->cur, buf->cur_idx)->base << TOPA_SHIFT); > } At this point, ->base is still a 40-bit (or 36-bit before this patch) type. If it has anything in the high 12 bits, a <