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Fri, 6 Nov 2026 05:32:56 +0000 Message-ID: Date: Thu, 5 Nov 2026 21:32:53 -0800 User-Agent: Mozilla Thunderbird From: "Chang S. Bae" Subject: Re: [PATCH v8 01/20] KVM: x86: Extend VCPU registers for EGPRs To: Jim Mattson , "Chang S. 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> > However, according to the Intel APX Architecture Specification (rev. 9.0), > section 3.1.4.1.1 and Table 3.7, R16-R31 are unchanged on INIT: > > The main difference between EGPRs and legacy GPRs, is that EGPRs are not > enabled by default (specifically XCR0-enabled) in 64-bit mode, and their > INIT behavior is XMM-like; in that EGPRs and many other XSAVE-enabled > register states are un-changed on INIT events as shown in Table 3.7. > > By extending NR_VCPU_GENERAL_PURPOSE_REGS to include VCPU_REGS_R16 through > VCPU_REGS_R31 without updating kvm_vcpu_reset(), KVM will erroneously zero > R16-R31 when init_event is true. Appreciate the review! This was overlooked since switched away from XSAVE to the VCPU cache. Initially, I thought okay to keep along with other XSTATEs: The specification deliberately scopes out some areas. For example, Sections 3.1.4.4.2–7 note that initialization and reset behaviors follow existing XSTATE conventions. Yes, you're right. The reset needs to be adjusted. Thanks, Chang