From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 451E3C4332F for ; Fri, 23 Dec 2022 09:12:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236150AbiLWJMg convert rfc822-to-8bit (ORCPT ); Fri, 23 Dec 2022 04:12:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46918 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236051AbiLWJM3 (ORCPT ); Fri, 23 Dec 2022 04:12:29 -0500 Received: from bg4.exmail.qq.com (bg4.exmail.qq.com [43.154.221.58]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8CADF3137A; Fri, 23 Dec 2022 01:12:26 -0800 (PST) X-QQ-mid: bizesmtp81t1671786703twus74c8 Received: from [192.168.3.2] ( [111.196.135.79]) by bizesmtp.qq.com (ESMTP) with id ; Fri, 23 Dec 2022 17:11:41 +0800 (CST) X-QQ-SSF: 01200000002000C0C000B00A0000000 X-QQ-FEAT: Qawnk02X7V/3XgZ2fM/jaE0BV64IhsybXxGbCgGgdSjq/pQgCE9fY4YxKS69I lDjwVxohnmpJtxN9bWL0Y5nR8nj2NtA0rw4Hxb2AjPqO+R1Ck65jLpoRASyyBBuqOjhXI0o bTNSgmMn0vS6HN5AfKKREc1jChYjO1pBJLE+Z+29XjVr6DbqivZoWNsZ3UnLf5XQmr+G/ft w3snpVgKBYGtqmYA7Lcs59ndbseq90J9dRVcaemaRNSJpOS1ZsP0pNwvMTtinmQwH+D4iPu DImOuCqmvDV8VsLzo0SNgk2vHCJ+rWdoJ0rWrZxXQjIBDZj9nk9VxKe9JxFz33/o/8KDYiV MsY1vptl+ym8KpBypAMM+t6v7Jf46ypq+O+WNkK X-QQ-GoodBg: 0 From: "Bin Meng" To: "Sergey Matyukevich" Subject: Re: [PATCH v3 0/3] serial: Add RISC-V support to the earlycon semihost driver Cc: linux-kernel , linux-riscv , linux-serial , aou , "catalin.marinas" , gregkh , jirislaby , palmer , "paul.walmsley" , linux , will , linux-arm-kernel Date: Fri, 23 Dec 2022 09:11:42 +0000 Message-Id: In-Reply-To: References: <20221209150437.795918-1-bmeng@tinylab.org> Reply-To: "Bin Meng" User-Agent: eM_Client/9.2.1222.0 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8BIT X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:tinylab.org:qybglogicsvr:qybglogicsvr3 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Sergey, On 2022/12/23 4:06:23, "Sergey Matyukevich" wrote: >Hi Bin, > >> RISC-V semihosting spec [1] is built on top of the existing Arm one; >> we can add RISC-V earlycon semihost driver easily. >> >> This series refactors the existing driver a little bit, to move smh_putc() >> variants in respective arch's semihost.h, then we can implement RISC-V's >> version in the riscv arch directory. >> >> Link: https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc [1] >> >> Changes in v3: >> - add #ifdef in the header to prevent from multiple inclusion >> - add forward-declare struct uart_port >> - add a Link tag in the commit message >> >> Changes in v2: >> - new patch: "serial: earlycon-arm-semihost: Move smh_putc() variants in respective arch's semihost.h" >> - Move the RISC-V implementation to semihost.h >> >> Bin Meng (3): >> serial: earlycon-arm-semihost: Move smh_putc() variants in respective >> arch's semihost.h >> riscv: Implement semihost.h for earlycon semihost driver >> serial: Rename earlycon semihost driver >> >> arch/arm/include/asm/semihost.h | 30 +++++++++++++++++++ >> arch/arm64/include/asm/semihost.h | 24 +++++++++++++++ >> arch/riscv/include/asm/semihost.h | 26 ++++++++++++++++ >> drivers/tty/serial/Kconfig | 14 ++++----- >> drivers/tty/serial/Makefile | 2 +- >> ...con-arm-semihost.c => earlycon-semihost.c} | 25 +--------------- >> 6 files changed, 89 insertions(+), 32 deletions(-) >> create mode 100644 arch/arm/include/asm/semihost.h >> create mode 100644 arch/arm64/include/asm/semihost.h >> create mode 100644 arch/riscv/include/asm/semihost.h >> rename drivers/tty/serial/{earlycon-arm-semihost.c => earlycon-semihost.c} (57%) > >Tested-by: Sergey Matyukevich > >Applied the patches on top of Linux 6.1 and tested earlycon logs from >RISC-V target in OpenOCD. > Thanks for your testing! Regards, Bin