From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 771F2302779 for ; Thu, 19 Feb 2026 21:12:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.15 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771535526; cv=none; b=dtx/YekjHHpjj2fCvBJhcZNOi4aZp1SmZIadTlnHNThLNFAtQVg9pMN4hC52Qndf6qsiAQNPLtS+KP0ogATsjMkCf5vyFjfWlEHXHga3Aw+rhyOEbsH9k6dxnqHvF8PIuuWGwmdOiDAdRsKM//3lZi1IgBcja8/WhfcesmTA+NQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771535526; c=relaxed/simple; bh=lg3ejPQtMKWWzljkektWAmW3n4uiwGNxl6VxYALybEA=; h=Message-ID:Subject:From:To:Cc:Date:In-Reply-To:References: Content-Type:MIME-Version; b=G8HHgbUShaLGvUEPTQWlKkjaWVxD623CphBATDz2Rw3gUJEc7SkUhw5tFXed8IXhs3bN1s+yhof0B/nQ/+NCEbd8fLd3M2rj2uV3IICrFAyo6h5xqbVIhmf1mUVq1y2Ohy3dkuSrAvJIesECaUHRJ74sjR7HZ8yYrXxE3lD2XAw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=So+IQwj6; arc=none smtp.client-ip=192.198.163.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="So+IQwj6" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1771535525; x=1803071525; h=message-id:subject:from:to:cc:date:in-reply-to: references:content-transfer-encoding:mime-version; bh=lg3ejPQtMKWWzljkektWAmW3n4uiwGNxl6VxYALybEA=; b=So+IQwj6MWgurq2cDvom/yXS3Lgvi66I4zQrsQeO2e0EJr/NvqrWc/8W Kf0eHQjd95wex9UJJVWlloHam3CxkQ6S0R8KdNb/j+LQ8OhZVuBdeRZUO 4RlKj5+KxuUZ6rE31BjOr07etdR3DeNVMO2KdAzJfy1rmVbwsKOuNA5ZV HV6NKi9oYhNbPiVMNlJd/yeLvAKEdiM2dARWZvTtSpjfOnsDvshcTzbpa uo6pExpBDEAOdLbVWEaHIzrLYPiNzUTlJLBqXQeHhQGC5ysq7TqE8MxwB uAsSzorZF4GSuqNQc8NJYD6D2d16uHN86zyRdZ++tzF18Emr+kFGHG1Tm g==; X-CSE-ConnectionGUID: KRDqPZ77SpOOhOyc/ZuBmA== X-CSE-MsgGUID: cEnr+azXS4+olf/Nfcrj9Q== X-IronPort-AV: E=McAfee;i="6800,10657,11706"; a="72733364" X-IronPort-AV: E=Sophos;i="6.21,300,1763452800"; d="scan'208";a="72733364" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Feb 2026 13:12:04 -0800 X-CSE-ConnectionGUID: +gx/+GTOTdS69VZLCpzEjg== X-CSE-MsgGUID: /RNKPMaoQVuOr4PqyYpmmA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,300,1763452800"; d="scan'208";a="219661659" Received: from unknown (HELO [10.241.243.83]) ([10.241.243.83]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Feb 2026 13:12:05 -0800 Message-ID: Subject: Re: [PATCH v3 15/21] sched/cache: Disable cache aware scheduling for processes with high thread counts From: Tim Chen To: Madadi Vineeth Reddy Cc: Peter Zijlstra , Ingo Molnar , K Prateek Nayak , "Gautham R . Shenoy" , Vincent Guittot , Chen Yu , Juri Lelli , Dietmar Eggemann , Steven Rostedt , Ben Segall , Mel Gorman , Valentin Schneider , Hillf Danton , Shrikanth Hegde , Jianyong Wu , Yangyu Chen , Tingyin Duan , Vern Hao , Vern Hao , Len Brown , Aubrey Li , Zhao Liu , Chen Yu , Adam Li , Aaron Lu , Tim Chen , Josh Don , Gavin Guo , Qais Yousef , Libo Chen , linux-kernel@vger.kernel.org Date: Thu, 19 Feb 2026 13:12:04 -0800 In-Reply-To: <6721ce77-c8b5-4fb3-b133-282b31ee6af2@linux.ibm.com> References: <34817728117f513084f39a99e18ea9a18cbfd3ae.camel@linux.intel.com> <6721ce77-c8b5-4fb3-b133-282b31ee6af2@linux.ibm.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.58.1 (3.58.1-1.fc43) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Thu, 2026-02-19 at 07:58 +0530, Madadi Vineeth Reddy wrote: > On 19/02/26 03:14, Tim Chen wrote: > > On Wed, 2026-02-18 at 23:24 +0530, Madadi Vineeth Reddy wrote: > > > On 11/02/26 03:48, Tim Chen wrote: > > > > From: Chen Yu > > > >=20 > > > >=20 > > [ .. snip ..] > >=20 > > > > =20 > > > > diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c > > > > index d1145997b88d..86b6b08e7e1e 100644 > > > > --- a/kernel/sched/fair.c > > > > +++ b/kernel/sched/fair.c > > > > @@ -1223,6 +1223,19 @@ static inline bool valid_llc_buf(struct sche= d_domain *sd, > > > > return valid_llc_id(id); > > > > } > > > > =20 > > > > +static bool exceed_llc_nr(struct mm_struct *mm, int cpu) > > > > +{ > > > > + int smt_nr =3D 1; > > > > + > > > > +#ifdef CONFIG_SCHED_SMT > > > > + if (sched_smt_active()) > > > > + smt_nr =3D cpumask_weight(cpu_smt_mask(cpu)); > > > > +#endif > > > > + > > > > + return !fits_capacity((mm->sc_stat.nr_running_avg * smt_nr), > > > > + per_cpu(sd_llc_size, cpu)); > > >=20 > > >=20 > > > On Power10/Power11 with SMT4 and LLC size of 4, this check > > > effectively disables cache-aware scheduling for any process. > >=20 > > There are 4 cores per LLC, with 4 SMT per core? In that case, once we h= ave more than > > 4 running threads and there's another idle LLC available, seems > > like putting the additional thread on a different LLC is the > > right thing to do as threads sharing a core will usually be much > > slower. > >=20 > > But when number of threads are under 4, we should still be > > doing aggregation. > >=20 > > Perhaps I am misunderstanding your topology. >=20 > There is only one core per LLC whose size is 4 CPUs. > So, mm->sc_stat.nr_running_avg can't be >=3D 1 for > cache aware scheduling to be enabled. If there is only 1 core, and mm->sc_stat.nr_running_avg > 1, wouldn't it be better to spread the tasks among the cores with normal load balance, instead of having threads aggregated fighting for the resource of a single core, i.e. run without cache aware scheduling? Tim=20 >=20 > Thanks, > Vineeth >=20 > >=20 > > Tim > >=20 > > >=20 > > > I raised this point in v1 as well. Increasing the threshold > > > doesn't seem like a viable solution either, as that would regress > > > hackbench/ebizzy. > > >=20 > > > Is there a way to make this useful for architectures with small LLC > > > sizes? One possible approach we were exploring is to have LLC at a > > > hemisphere level that comprise multiple SMT4 cores. > > >=20 > > > Thanks, > > > Vineeth