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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9b30f58991sm90413066b.159.2024.10.25.10.26.52 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 25 Oct 2024 10:26:55 -0700 (PDT) Message-ID: Date: Fri, 25 Oct 2024 19:26:52 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 4/4] arm64: dts: qcom: qcs615: add the APPS SMMU node To: Qingqing Zhou , Konrad Dybcio , andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, robimarko@gmail.com, will@kernel.org, robin.murphy@arm.com, joro@8bytes.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev References: <20241015081603.30643-1-quic_qqzhou@quicinc.com> <20241015081603.30643-5-quic_qqzhou@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: SCbDLvvHZicmTyy3eAnAifXnYwICpMGO X-Proofpoint-GUID: SCbDLvvHZicmTyy3eAnAifXnYwICpMGO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 impostorscore=0 priorityscore=1501 mlxlogscore=999 bulkscore=0 lowpriorityscore=0 spamscore=0 phishscore=0 malwarescore=0 adultscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410250133 On 23.10.2024 7:48 AM, Qingqing Zhou wrote: > > > 在 10/18/2024 2:20 PM, Qingqing Zhou 写道: >> >> >> 在 10/18/2024 4:05 AM, Konrad Dybcio 写道: >>> On 15.10.2024 10:16 AM, Qingqing Zhou wrote: >>>> Add the APPS SMMU node for QCS615 platform. Add the dma-ranges >>>> to limit DMA address range to 36bit width to align with system >>>> architecture. >>>> >>>> Signed-off-by: Qingqing Zhou >>>> --- >>>> arch/arm64/boot/dts/qcom/qcs615.dtsi | 74 ++++++++++++++++++++++++++++ >>>> 1 file changed, 74 insertions(+) >>>> >>>> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi >>>> index 027c5125f36b..fcba83fca7cf 100644 >>>> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi >>>> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi >>>> @@ -379,6 +379,7 @@ >>>> soc: soc@0 { >>>> compatible = "simple-bus"; >>>> ranges = <0 0 0 0 0x10 0>; >>>> + dma-ranges = <0 0 0 0 0x10 0>; >>>> #address-cells = <2>; >>>> #size-cells = <2>; >>>> >>>> @@ -524,6 +525,79 @@ >>>> reg = <0x0 0x0c3f0000 0x0 0x400>; >>>> }; >>>> >>>> + apps_smmu: iommu@15000000 { >>>> + compatible = "qcom,qcs615-smmu-500", "qcom,smmu-500", "arm,mmu-500"; >>>> + reg = <0x0 0x15000000 0x0 0x80000>; >>>> + #iommu-cells = <2>; >>>> + #global-interrupts = <1>; >>>> + >>>> + interrupts = , >>>> + , >>>> + , >>> >>> The list seems perfectly sorted, which is suspicious.. if we set >>> i = n - #global-interrupts, interrupt[i] signifies an error in the i-th >>> context bank. If the order is wrong, we'll get bogus reports >> Thanks for the review, the list refers to Qualcomm Interrupts design spec, checking this platform again, the list is right, first line is global interrupt and the others are context interrupts with right order. > Hi Konrad, > Hope above comments explain your question. If no more questions from you, I will post the next version. Thanks. Sorry, forgot to reply. I was able to confirm this is just a happy coincidence with the numbers. Konrad