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[199.106.103.254]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2be2f0d1849sm411313eec.28.2026.03.03.15.17.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 03 Mar 2026 15:17:32 -0800 (PST) Message-ID: Date: Tue, 3 Mar 2026 15:17:31 -0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 1/2] dt-bindings: phy: qcom: Add CSI2 C-PHY/DPHY schema To: Bryan O'Donoghue , Bryan O'Donoghue , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong Cc: Vladimir Zapolskiy , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260226-x1e-csi2-phy-v3-0-11e608759410@linaro.org> <20260226-x1e-csi2-phy-v3-1-11e608759410@linaro.org> <4pFL6wOeTKUt-Zq4YbjqJdacMgUIPSYJD-4-5DcIMEZ1sM7JsNFYcSv1bd7ZRVOklTsmkEfxM2b6tTflmiECNQ==@protonmail.internalid> <03b44922-72d5-465b-96e1-97a19655e97d@kernel.org> <4440a3a8-7281-4bea-bb84-7a9d19ef7ce9@oss.qualcomm.com> <2a1155bd-7dc5-4ed8-b1eb-ddfa483c75ca@oss.qualcomm.com> <4fea7117-ebd3-4279-9973-3ac4f2a78835@linaro.org> Content-Language: en-US From: Vijay Kumar Tumati In-Reply-To: <4fea7117-ebd3-4279-9973-3ac4f2a78835@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=JqL8bc4C c=1 sm=1 tr=0 ts=69a76c0d cx=c_pps a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=w7-7VXPaYEwSs5UKW_AA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=bBxd6f-gb0O0v-kibOvt:22 X-Proofpoint-ORIG-GUID: hf44BqH-3fro_kMptGspmrikMFlAnPFj X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzAzMDE5MiBTYWx0ZWRfXxuoHzGDqnsB0 WmnHwsZYazzbOornYSLN9gAct6SALqBMb3q+TRXBVZzb+RB8azzi3TjuCNuZeGhFOYZ2OO4wG1I +5b3HjQ1PVNdO3/NG4inEK8taj931bif6RUzEJc+Pypx9444fMyJyPr/5+tl5xVgJoh7pG7FaD0 x8xwY/7flTGAJTgyZp2ALagt9BKvCRGgM6HZG3haiblvNasCltxWA9Is2UTD97jhft03/BPUbD5 3mPowup1hQm41f9o0/bMx2QKed0repQKvUgEfOfD4bPpHvje5pZppM5KdYDLCPsMjxcPIpJ6E5c C31cozynfdmPEeJYinRQQDuTjbHFmowjok2adC1W/nuaFBDXjYInDYvPuMelzFNY9Loy5DINsJo 10AkeKp6X+bsSh9lwsn00vqWj6xFWnpW9tQTIkdr8f2RY6YRkOmV06rUkCMTlL6wip9mX8LM75S 19M73wlZ1uurRlcn9hw== X-Proofpoint-GUID: hf44BqH-3fro_kMptGspmrikMFlAnPFj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-03_03,2026-03-03_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 priorityscore=1501 lowpriorityscore=0 clxscore=1015 phishscore=0 spamscore=0 suspectscore=0 malwarescore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603030192 On 3/3/2026 2:53 PM, Bryan O'Donoghue wrote: > On 03/03/2026 18:58, Vijay Kumar Tumati wrote: >>>> - TITAN_TOP_GDSC >>>> - MXC >>>> - MMCX >>>> - MXA - first time I've heard of this rail, from memory I don't >>>> remember >>>>          having seen this in ipcat when I could do so. >>> MCX and MMCX are comminly required power domains across the PHYs but >>> a subset of PHYs have the dependency on MXA. >> Actually, it's a bit more complicated on this target as >> cam_cc_cphy_rx_clk_src also depends on MXA, which means all the CBCs >> connected this RCG do as well. > > Right but that's something to model in the clock-controller then not the > PHY. > > i.e. if a clock depends on MXA then the clock controller should > represent that dependency - not the PHY that depends on the clock. > > camcc on hamoa looks like this > >                 camcc: clock-controller@ade0000 { >                         compatible = "qcom,x1e80100-camcc"; >                         reg = <0 0x0ade0000 0 0x20000>; >                         clocks = <&gcc GCC_CAMERA_AHB_CLK>, >                                  <&bi_tcxo_div2>, >                                  <&bi_tcxo_ao_div2>, >                                  <&sleep_clk>; >                         power-domains = <&rpmhpd RPMHPD_MXC>, >                                         <&rpmhpd RPMHPD_MMCX>; >                         required-opps = <&rpmhpd_opp_low_svs>, >                                         <&rpmhpd_opp_low_svs>; >                         #clock-cells = <1>; >                         #reset-cells = <1>; >                         #power-domain-cells = <1>; >                 }; > > So... we may need to add MXA here, probably do based on what you've said > but I believe TITAN_TOP_GDSC is the only power-domain we need to list > for the PHYs themselves, as what you've described above is a clock power > dependency which we basically already capture in the clock controller - > absent the MXA - which is apparently always on... > > Sidenote, is MXA required for videocc too ? > >                 videocc: clock-controller@aaf0000 { >                         compatible = "qcom,x1e80100-videocc"; >                         reg = <0 0x0aaf0000 0 0x10000>; >                         clocks = <&bi_tcxo_div2>, >                                  <&gcc GCC_VIDEO_AHB_CLK>; >                         power-domains = <&rpmhpd RPMHPD_MMCX>, >                                         <&rpmhpd RPMHPD_MXC>; >                         required-opps = <&rpmhpd_opp_low_svs>, >                                         <&rpmhpd_opp_low_svs>; >                         #clock-cells = <1>; >                         #reset-cells = <1>; >                         #power-domain-cells = <1>; >                 }; > > --- > bod Well, the current upstream clock driver (at least for CAMCC) enables these power domains at the min level but they do not scale them. So even if we add MXA in the camcc device, they won't be scaled per the PHY core clocks. For example, if you are running PHY at TURBO, the power supplies may still be at the min level or scaled individually according to the requests from other sub systems. If we need this to be controlled from the clock driver directly, we will need multiple performance states for the TOP GDSC.However, this GDSC enables all the clocks in Titan, each with it's own voltage rail connections, so a bit complicated but can be discussed with the clock driver team. Sorry, I do not know about videocc. Thanks, Vijay.