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Thu, 5 Nov 2026 08:51:18 +0800 (GMT+08:00) Message-ID: Date: Thu, 5 Nov 2026 08:51:14 +0800 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Cc: shawn.lin@rock-chips.com, Alexey Charkov , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com Subject: Re: [PATCH v8 7/9] PCI: dw-rockchip: Add pme_turn_off support To: Sebastian Reichel , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , Philipp Zabel , Jingoo Han , Liam Girdwood , Mark Brown , "Yury Norov (NVIDIA)" , Nicolas Frattaroli References: <20261105-rockchip-pcie-system-suspend-v8-0-0434b4f373bc@collabora.com> <20261105-rockchip-pcie-system-suspend-v8-7-0434b4f373bc@collabora.com> From: Shawn Lin In-Reply-To: <20261105-rockchip-pcie-system-suspend-v8-7-0434b4f373bc@collabora.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-HM-Tid: 0aa1a930507d03a4kunm7b7b2c6111ce48 X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWRgWCB1ZQUpXWS1ZQUlXWQ8JGhUIEh9ZQVlDSBlJVkgaQkNKTR9MSR5CHlYVFA kWGhdVEwETFhoSFyQUDg9ZV1kYEgtZQVlNSlVKTk9VSk9VQ01ZV1kWGg8SFR0UWUFZT0tIVUpLSU 9PT0hVSktLVUpCS0tZBg++ DKIM-Signature: a=rsa-sha256; b=ed/W9pMIXtu5yRJRX83WEULDuzONtKh2KGDEcb97UklFlrvv5C3CMhCccjEFUhMlchyOLJAprM686mxfc7tWjHzWqBUhRRM8shTlsrCQnZUsxYIU1rtFwSDJojCUXPr6oPLLxEocusN0/jY3UmO7AmWWmEB0XONgEidRDNO+fjc=; c=relaxed/relaxed; s=default; d=rock-chips.com; v=1; bh=+2E6dr27WqMqCaaLamwNn6gQm66M2Zv099gvqTnexrw=; h=date:mime-version:subject:message-id:from; 在 2026/11/05 星期四 7:47, Sebastian Reichel 写道: > Prepare Rockchip PCIe controller for system suspend support by > adding the PME turn off operation. > > Signed-off-by: Sebastian Reichel > --- > drivers/pci/controller/dwc/pcie-dw-rockchip.c | 47 +++++++++++++++++++++++++++ > 1 file changed, 47 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c > index 0e26abc50920..7933c50df340 100644 > --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c > +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c > @@ -47,6 +47,10 @@ > #define PCIE_CLIENT_ENABLE_LTSSM FIELD_PREP_WM16(BIT(2), 1) > #define PCIE_CLIENT_DISABLE_LTSSM FIELD_PREP_WM16(BIT(2), 0) > > +/* Interrupt Status Register for Received Messages */ > +#define PCIE_CLIENT_INTR_STATUS_MSG_RX 0x04 > +#define PME_TO_ACK BIT(9) > + > /* Interrupt Status Register Related to Legacy Interrupt */ > #define PCIE_CLIENT_INTR_STATUS_LEGACY 0x8 > > @@ -71,6 +75,11 @@ > #define PCIE_CLKREQ_READY FIELD_PREP_WM16(BIT(0), 1) > #define PCIE_CLKREQ_NOT_READY FIELD_PREP_WM16(BIT(0), 0) > #define PCIE_CLKREQ_PULL_DOWN FIELD_PREP_WM16(GENMASK(13, 12), 1) > +#define PME_READY_ENTER_L23 BIT(3) > + > +/* Message Request Register */ > +#define PCIE_CLIENT_MSG_GEN 0x34 > +#define PME_TURN_OFF FIELD_PREP_WM16(BIT(4), 1) > > /* RASDES TBA information */ > #define PCIE_CLIENT_CDM_RASDES_TBA_INFO_CMN 0x154 > @@ -439,8 +448,46 @@ static int rockchip_pcie_host_init(struct dw_pcie_rp *pp) > return 0; > } > > +static void rockchip_pcie_pme_turn_off(struct dw_pcie_rp *pp) > +{ > + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > + struct rockchip_pcie *rockchip = to_rockchip_pcie(pci); > + struct device *dev = rockchip->pci.dev; > + u32 status; > + int ret; > + > + /* 1. Broadcast PME_Turn_Off Message, bit 4 self-clear once done */ > + rockchip_pcie_writel_apb(rockchip, PME_TURN_OFF, PCIE_CLIENT_MSG_GEN); > + ret = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_MSG_GEN, > + status, !(status & BIT(4)), PCIE_PME_TO_L2_TIMEOUT_US / 10, > + PCIE_PME_TO_L2_TIMEOUT_US); > + if (ret) { > + dev_warn(dev, "Failed to send PME_Turn_Off\n"); > + return; > + } > + > + /* 2. Wait for PME_TO_Ack, bit 9 will be set once received */ > + ret = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_INTR_STATUS_MSG_RX, > + status, status & BIT(9), PCIE_PME_TO_L2_TIMEOUT_US / 10, > + PCIE_PME_TO_L2_TIMEOUT_US); > + if (ret) { > + dev_warn(dev, "Failed to receive PME_TO_Ack\n"); > + return; > + } > + > + /* 3. Clear PME_TO_Ack and Wait for ready to enter L23 message */ > + rockchip_pcie_writel_apb(rockchip, PME_TO_ACK, PCIE_CLIENT_INTR_STATUS_MSG_RX); > + ret = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_POWER_CON, > + status, status & PME_READY_ENTER_L23, > + PCIE_PME_TO_L2_TIMEOUT_US / 10, > + PCIE_PME_TO_L2_TIMEOUT_US); > + if (ret) > + dev_err(dev, "Failed to get ready to enter L23 message\n"); > +} This is a question for the DWC core: should we change dw_pcie_host_ops::pme_turn_off() to return a value instead of silently ignoring a failure? Looking at pcie-designware-host.c, we have: if (pci->pp.ops->pme_turn_off) { pci->pp.ops->pme_turn_off(&pci->pp); } else { ret = dw_pcie_pme_turn_off(pci); if (ret) return ret; } The handling feels asymmetric. If ->pme_turn_off fails, shouldn't we abort dw_pcie_suspend_noirq as well? Other than that, this patch looks good to me in current shape, Reviewed-by: Shawn Lin We can further discuss the callback's return value issue on top. > + > static const struct dw_pcie_host_ops rockchip_pcie_host_ops = { > .init = rockchip_pcie_host_init, > + .pme_turn_off = rockchip_pcie_pme_turn_off, > }; > > /* >