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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-adfade680d4sm186158466b.10.2025.06.14.11.50.39 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 14 Jun 2025 11:50:41 -0700 (PDT) Message-ID: Date: Sat, 14 Jun 2025 20:50:39 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v9 01/10] clk: qcom: clk-alpha-pll: Add support for dynamic update for slewing PLLs To: Taniya Das , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Will Deacon , Catalin Marinas Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org References: <20250612-qcs615-mm-v9-clock-controllers-v9-0-b34dc78d6e1b@quicinc.com> <20250612-qcs615-mm-v9-clock-controllers-v9-1-b34dc78d6e1b@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20250612-qcs615-mm-v9-clock-controllers-v9-1-b34dc78d6e1b@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: -GU1fyiEx2YpypjPxRHE4EoGt8tXcNav X-Authority-Analysis: v=2.4 cv=BoedwZX5 c=1 sm=1 tr=0 ts=684dc483 cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=6IFa9wvqVegA:10 a=COk6AnOGAAAA:8 a=b3DFIE2h8Nkn-kLj-EYA:9 a=QEXdDO2ut3YA:10 a=dawVfQjAaf238kedN5IG:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: -GU1fyiEx2YpypjPxRHE4EoGt8tXcNav X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjE0MDE1OCBTYWx0ZWRfX4yPoHjFXycH7 xVT6JwJJ72e/wwQ1FmkGwW9MTzijiX52l19L6emBPCw1g8eR5wR+kG4rhy75RSxQKutkaH2Z3vz A0xrHXc2IhivhSq6QV0rIlBXbDhbAKXz0oQ3tmCjDrFEH8yMxwlbKY6G1+KXQZ8VkZsfFmixGky tzhyb6to4tUC4gJkuY82GkOfHmTREQHIJ9ga3yniutXFBy4jphcCJPc98Io+J3NL7JKlC0FHhVt fx6sh6xkgXSNDFlDnaAw98paAYKTwXYKXmaorMo5NgEMhxuxU4E+HeT3cQ22cNY9De/MjKJXgqn wpsQ+UcxFCDheTwXoRSLu7rW4008ZM0a49AT3WQYCgT3Vqfgf1nd3Pq8opR+1w8KuMxt6wnPGFJ TuI5DPecLV4+nG9ouRl69izCZOV1RkGMud7/occau0m6c51p4zH1V3H1dC2P3gHdLH83Cu7z X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-06-14_07,2025-06-13_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 mlxscore=0 adultscore=0 phishscore=0 lowpriorityscore=0 mlxlogscore=999 bulkscore=0 malwarescore=0 priorityscore=1501 clxscore=1015 spamscore=0 suspectscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506140158 On 6/12/25 11:55 AM, Taniya Das wrote: > The alpha PLLs which slew to a new frequency at runtime would require > the PLL to calibrate at the mid point of the VCO. Add the new PLL ops > which can support the slewing of the PLL to a new frequency. > > Reviewed-by: Imran Shaik > Signed-off-by: Taniya Das > --- > drivers/clk/qcom/clk-alpha-pll.c | 170 +++++++++++++++++++++++++++++++++++++++ > drivers/clk/qcom/clk-alpha-pll.h | 1 + > 2 files changed, 171 insertions(+) > > diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c > index cec0afea8e446010f0d4140d4ef63121706dde47..5e4a755b849970281e7742ef83219b7eeaa406c3 100644 > --- a/drivers/clk/qcom/clk-alpha-pll.c > +++ b/drivers/clk/qcom/clk-alpha-pll.c > @@ -2960,3 +2960,173 @@ const struct clk_ops clk_alpha_pll_regera_ops = { > .set_rate = clk_zonda_pll_set_rate, > }; > EXPORT_SYMBOL_GPL(clk_alpha_pll_regera_ops); > + > +static int clk_alpha_pll_slew_update(struct clk_alpha_pll *pll) > +{ > + int ret; > + u32 val; > + > + regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, PLL_UPDATE); There's an ever sweeter sugar-syntax for this case - regmap_set_bits() > + regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); > + > + ret = wait_for_pll_update(pll); > + if (ret) > + return ret; > + /* > + * Hardware programming mandates a wait of at least 570ns before polling the LOCK > + * detect bit. Have a delay of 1us just to be safe. > + */ > + mb(); Since you read the value of PLL_MODE back, the barrier is unnecessary [...] > + > + regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); > + regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), lower_32_bits(a)); > + regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), upper_32_bits(a)); > + > + /* Ensure that the write above goes before slewing the PLL */ > + mb(); Here however, the write may not arrive at the clock controller before you proceed to slew_update() > + > + if (clk_hw_is_enabled(hw)) > + return clk_alpha_pll_slew_update(pll); > + > + return 0; > +} > + > +/* > + * Slewing plls should be bought up at frequency which is in the middle of the > + * desired VCO range. So after bringing up the pll at calibration freq, set it > + * back to desired frequency(that was set by previous clk_set_rate). > + */ > +static int clk_alpha_pll_calibrate(struct clk_hw *hw) > +{ > + unsigned long calibration_freq, freq_hz; > + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); > + struct clk_hw *parent; > + const struct pll_vco *vco; > + u32 l; > + int rc; > + u64 a; A reverse-Christmas-tree sorting would be nice Konrad