From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8F5AB1A2630 for ; Fri, 19 Dec 2025 03:32:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766115123; cv=none; b=fNW5BxxKJmYTnuJCSKqvfujLbRKJ3PhKxZBgfm8Okx1T1KNoPpVs3s/rnqYwRuKL+gNnG+NC97KMj4aURVjW2Y8kjXhhi9dMMaIDVDd86lz6ZD4iSa/Iryl/KXxBoix5xO6GP44tTJYEaQV0b3yZh5ljJQ+2RxNycwBpUJQiDxg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766115123; c=relaxed/simple; bh=h72DaDq4OFEjfcUtWloNwRS2+Jen9IPj3Fg84jOhxiQ=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=lwgkmfaA+dfPNzYHgGQLwLWISievPNYvQOlifFylIJu91HjxH/eM38MpK2TDbCUeYUor+yq1btUl358+6K0oIxt39lImM1vXJ80jKSs8nJ5Bg2trK7609L8hD1o5vIFCk7kivNvHTJrfIJqcA7YVHGIgqcEMn61Rq2FzTpkUFQw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=SiAmNsNo; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=SMnQZQbV; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="SiAmNsNo"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="SMnQZQbV" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5BJ2ODZH3033952 for ; Fri, 19 Dec 2025 03:32:00 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= x56mI00illQfl6akd6y5SiCn/TcBzWlA1UnduG5C/0I=; b=SiAmNsNo2l8e5oCT BefH1n4w1tDlpfDUu2PyKVNGGlhNMP7CesegN4NZhBMfqteTbURIkoYxxhp4oUWo yuahr3gBmtzCY1Nv8DYLigBDRAMOElcHdnp3Owc3/a+3v6voNSJNW3OYzXHN0jgu ltRYR72xMiJDYE9okt+buUu16ekLEwWEZVVOocX2iaMegRG8cOhD7PZDITAAitz7 M6PwLuJfRfJ0uWJQhMyl6sn8eIWEibX31ZlJosg4ApyIvHeUZ2B7dLQbODwtspno ELpnWtFMKSeoIJZwQIzUUMOPUP8tJFkZ7FBNPVbtkqXV7itA6SZvOYXuU6QC2Swa 86CnZg== Received: from mail-pl1-f199.google.com (mail-pl1-f199.google.com [209.85.214.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4b4r2es1r1-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 19 Dec 2025 03:32:00 +0000 (GMT) Received: by mail-pl1-f199.google.com with SMTP id d9443c01a7336-2a0b7eb0a56so35677205ad.1 for ; Thu, 18 Dec 2025 19:32:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1766115119; x=1766719919; darn=vger.kernel.org; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=x56mI00illQfl6akd6y5SiCn/TcBzWlA1UnduG5C/0I=; b=SMnQZQbVelNwy8dPIJO8HOmR+yIC9PcFGqXVE7QAXQuIA02XU68pDzQNfV+U4roz9Z hoB2LUtUG69ZeREsuTI8Hz14yMIZ5GlGwAiHHwDEjMVXiv1zpLCMgEr5TONjCm2q9Mi7 iMaR49vsDX0ir316iHAZ9E4dH0mmMJnIpqEt9zt3IhVxr+XqyVl6UPTomwsXa0Hg8UL+ dCPvs2LgRYqXaenKmlKV8qssLGqtebJNIX4d/8pxnxlNUCAzfivbmji03GYLSdhXTPu5 NkWt5eSNe4XY7qnDT+snKsQ2C2uf1qwBgMIrBc0ZZZauyABqnA+RH6174rxfm+6F3sOf 2v4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1766115119; x=1766719919; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :x-gm-gg:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=x56mI00illQfl6akd6y5SiCn/TcBzWlA1UnduG5C/0I=; b=kB4uMv1XIaiP6tZCTAXXOiqHAbh3g7xoZbPg1R/ObGkKt+/MLnWews2BPQ/79MzcPv 6nVhyVrOI8kG7J+D+0cbOqJF10C8bOOJdLJWgQ4gY+p5NwdX9S6njnf0oo3D8BqvZlUS Qs4RZnFfpnFuU1gLiqtcQhC/8T3U/n2AAW+zR3hltPBKOjPpJ59SndiVJv+XsCbSzBgr zbKYLkAKyQJr3EOZNcEVZTOtNxleeVXm+NDAZbrPff5ao/fEHSggnuXvUJMfhask8zAA AZ46ETsgLK8Ykqp2j6FBjKRw9voWIzQZtBD83pNgLuwxD+JO4Q7V4EJXv2UTT2JmLwl7 yxBA== X-Forwarded-Encrypted: i=1; AJvYcCXjxslnOLWR6w7SwyRSqB7whulTg2Wejcs/S9Syx627N5TRdbE+7Yz2PWKJ2bFtAl6lZpXE2axbuhK1V/s=@vger.kernel.org X-Gm-Message-State: AOJu0YwZchn9WpubbE0Nro444SvyGl/WuEfNmP+xcH6o6RBVFAXSLa3c LWKoNx+DHmLumbNi+jXUg3ACCA4Ey58a3LMmujQJiuLpjY8Q14C3wdEU1KevednWhvLyMk5CRGE ix3nkyBHA9TxlxV1SYNLCyZc12f3jDIzqU4tp37f+UVi5gwsTrjbNXVppY5l+hN9GEaY= X-Gm-Gg: AY/fxX5RNE67QGG4xEoDgHeD1iVJOyacEHV/RmDy9rxeogaZBL236HRTmHan3HyZUUF QbBO9UJkk6pcy/d0SVAL4UGfx3H0kQCgTouKsMvqyKBxWebZB0pd+TNayvQnOxaP3HQVZDgxqHH 3qhc41Pdwd/OHNTZXhFK2GJDemDeDDK+txkSOQ7gmSviCJXpcjrVYtSju83COyq8G3QGYcr0DBc OKkMq7zmg0iUm+RYvUuzng5E1hhol8qvXQGiRVTDTSXWgk3wsXEYbCcwmsrAP2t57oRQN5qcKSn 7ZmHBcCh8mOkixCYuANEGYCF0thV7cAPJtH8O5y3VwX2WO1rlCMAKpGOtYclpMP6lWBgh5gftbM hOtLPUP/vwtSiFlePfzsEUlSyrNKkSDosVPsflErr2WSCGiCsgPwtxvTbE/bmJI9nEaZwU82UOg Q= X-Received: by 2002:a17:902:e808:b0:2a0:9d0f:b1ed with SMTP id d9443c01a7336-2a2f23277f6mr12926555ad.24.1766115118409; Thu, 18 Dec 2025 19:31:58 -0800 (PST) X-Google-Smtp-Source: AGHT+IHjXE0gcT+I/3vqOt36tBsA13k0DFicCrebhOEGFHe67ozPzsjJOg7E/124merh6ZejBtJKhg== X-Received: by 2002:a17:902:e808:b0:2a0:9d0f:b1ed with SMTP id d9443c01a7336-2a2f23277f6mr12926245ad.24.1766115117770; Thu, 18 Dec 2025 19:31:57 -0800 (PST) Received: from [10.133.33.174] (tpe-colo-wan-fw-bordernet.qualcomm.com. [103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a2f3d5d20dsm6838525ad.67.2025.12.18.19.31.52 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 18 Dec 2025 19:31:57 -0800 (PST) Message-ID: Date: Fri, 19 Dec 2025 11:31:49 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 1/3] coresight: tpda: add sysfs nodes for tpda cross-trigger configuration To: Suzuki K Poulose , Mike Leach , James Clark , Alexander Shishkin , Tingwei Zhang Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Tao Zhang References: <20251028-configure_tpda_reg-v4-0-23000805d21d@oss.qualcomm.com> <20251028-configure_tpda_reg-v4-1-23000805d21d@oss.qualcomm.com> Content-Language: en-US From: Jie Gan In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: RSt2lYLpXASWFmvhFhSOluXvmtxdG0RD X-Proofpoint-ORIG-GUID: RSt2lYLpXASWFmvhFhSOluXvmtxdG0RD X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjE5MDAyOCBTYWx0ZWRfX3j1Z9RV6Kkxm Kfvyjkx0yZ289fk7YgLONpUVtcvOKen+GRIF1d2r+0QQNqLdbVA+qA2HU24cqqJqbc/7d1MKY9+ juHAiQrIicb/sn+tFQZigpoubM/9WqCPflrMf43fhZInYPxueV1ESbQ3W4Uo7ri4kCnf81oPZmb FDZevGFR0vBjeeXk1acDAiaLHhhbxob7nXcdPWTLw9TeggSrGlrKUSnbFt+n1GM5bFdGBlCQJSt Dkj7WCXEi4FGvNIj2FYe1Kolz3IYIlFpe/RuvTJ8LVuTx/ne4kzk4gw21Aby5Vd1Bjf5UljC1WN 1fGT1avRI6exWGDWTZVwYggF9aYcCMf3YSvAYBn/8FIfgCgxxy8ONXz41RSJInFaTer4KEdHDLn ctRVRBcwqaTnXmv48ani3JT6Vd+pJwM3NiJcAzxBa0q7AqMaelOTwCDIEagJXE9KobI52c3Tk40 fZ/Ad7fB8laiFV44FNg== X-Authority-Analysis: v=2.4 cv=Tp7rRTXh c=1 sm=1 tr=0 ts=6944c730 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=CvuRUKyVQJBZ2Q8Vu1IA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-19_01,2025-12-17_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 clxscore=1015 impostorscore=0 malwarescore=0 spamscore=0 phishscore=0 priorityscore=1501 lowpriorityscore=0 suspectscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512190028 On 12/18/2025 7:10 PM, Suzuki K Poulose wrote: > On 28/10/2025 02:02, Jie Gan wrote: >> From: Tao Zhang >> >> Introduce sysfs nodes to configure cross-trigger parameters for TPDA. >> These registers define the characteristics of cross-trigger packets, >> including generation frequency and flag values. >> >> Signed-off-by: Tao Zhang >> Reviewed-by: James Clark >> Co-developed-by: Jie Gan >> Signed-off-by: Jie Gan >> --- >>   .../ABI/testing/sysfs-bus-coresight-devices-tpda   |  43 ++++ >>   drivers/hwtracing/coresight/coresight-tpda.c       | 230 +++++++++++ >> ++++++++++ >>   drivers/hwtracing/coresight/coresight-tpda.h       |  27 ++- >>   3 files changed, 299 insertions(+), 1 deletion(-) >> >> diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices- >> tpda b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda >> new file mode 100644 >> index 000000000000..80e4b05a1ab4 >> --- /dev/null >> +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda >> @@ -0,0 +1,43 @@ >> +What:        /sys/bus/coresight/devices//trig_async_enable >> +Date:        October 2025 >> +KernelVersion:    6.19 >> +Contact:    Jinlong Mao , Tao Zhang >> , Jie Gan >> +Description: >> +        (RW) Enable/disable cross trigger synchronization sequence >> interface. >> + >> +What:        /sys/bus/coresight/devices//trig_flag_ts_enable >> +Date:        October 2025 >> +KernelVersion:    6.19 >> +Contact:    Jinlong Mao , Tao Zhang >> , Jie Gan >> +Description: >> +        (RW) Enable/disable cross trigger FLAG packet request interface. >> + >> +What:        /sys/bus/coresight/devices//trig_freq_enable >> +Date:        October 2025 >> +KernelVersion:    6.19 >> +Contact:    Jinlong Mao , Tao Zhang >> , Jie Gan >> +Description: >> +        (RW) Enable/disable cross trigger FREQ packet request interface. >> + >> +What:        /sys/bus/coresight/devices//freq_ts_enable >> +Date:        October 2025 >> +KernelVersion:    6.19 >> +Contact:    Jinlong Mao , Tao Zhang >> , Jie Gan >> +Description: >> +        (RW) Enable/disable the timestamp for all FREQ packets. >> + >> +What:        /sys/bus/coresight/devices//global_flush_req >> +Date:        October 2025 >> +KernelVersion:    6.19 >> +Contact:    Jinlong Mao , Tao Zhang >> , Jie Gan >> +Description: >> +        (RW) Set global (all ports) flush request bit. The bit >> remains set until a >> +        global flush request sequence completes. >> + >> +What:        /sys/bus/coresight/devices//cmbchan_mode >> +Date:        October 2025 >> +KernelVersion:    6.19 >> +Contact:    Jinlong Mao , Tao Zhang >> , Jie Gan >> +Description: >> +        (RW) Configure the CMB/MCMB channel mode for all enabled ports. >> +        Value 0 means raw channel mapping mode. Value 1 means channel >> pair marking mode. >> diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/ >> hwtracing/coresight/coresight-tpda.c >> index 333b3cb23685..a9a27bcc65a1 100644 >> --- a/drivers/hwtracing/coresight/coresight-tpda.c >> +++ b/drivers/hwtracing/coresight/coresight-tpda.c >> @@ -147,9 +147,37 @@ static void tpda_enable_pre_port(struct >> tpda_drvdata *drvdata) >>       u32 val; >>       val = readl_relaxed(drvdata->base + TPDA_CR); >> +    val &= ~TPDA_CR_MID; >>       val &= ~TPDA_CR_ATID; > > See, below. > >>       val |= FIELD_PREP(TPDA_CR_ATID, drvdata->atid); >> +    if (drvdata->trig_async) >> +        val |= TPDA_CR_SRIE; >> +    else >> +        val &= ~TPDA_CR_SRIE; >> +    if (drvdata->trig_flag_ts) >> +        val |= TPDA_CR_FLRIE; >> +    else >> +        val &= ~TPDA_CR_FLRIE; >> +    if (drvdata->trig_freq) >> +        val |= TPDA_CR_FRIE; >> +    else >> +        val &= ~TPDA_CR_FRIE; >> +    if (drvdata->freq_ts) >> +        val |= TPDA_CR_FREQTS; >> +    else >> +        val &= ~TPDA_CR_FREQTS; >> +    if (drvdata->cmbchan_mode) >> +        val |= TPDA_CR_CMBCHANMODE; >> +    else >> +        val &= ~TPDA_CR_CMBCHANMODE; > > Could we clear all of the bits that are configurable in one go in the > beginning and set the appropriate ones based on the setting ? i.e.: > > Do we really need to retain any values ? And if not, why not start > with a fresh set of values and avoid the read ? Got it. We can start with a clean value and set the required bits, without needing to read the register once. > >>       writel_relaxed(val, drvdata->base + TPDA_CR); >> + >> +    /* >> +     * If FLRIE bit is set, set the master and channel >> +     * id as zero >> +     */ >> +    if (drvdata->trig_flag_ts) >> +        writel_relaxed(0x0, drvdata->base + TPDA_FPID_CR); >>   } >>   static int tpda_enable_port(struct tpda_drvdata *drvdata, int port) >> @@ -265,6 +293,206 @@ static const struct coresight_ops tpda_cs_ops = { >>       .link_ops    = &tpda_link_ops, >>   }; >> +static ssize_t trig_async_enable_show(struct device *dev, >> +                      struct device_attribute *attr, >> +                      char *buf) >> +{ >> +    struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); >> + >> +    return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->trig_async); >> +} >> + >> +static ssize_t trig_async_enable_store(struct device *dev, >> +                       struct device_attribute *attr, >> +                       const char *buf, >> +                       size_t size) >> +{ >> +    struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); >> +    unsigned long val; >> + >> +    if (kstrtoul(buf, 0, &val)) >> +        return -EINVAL; >> + >> +    guard(spinlock)(&drvdata->spinlock); >> +    drvdata->trig_async = !!val; >> + > > > >> +    return size; >> +} >> +static DEVICE_ATTR_RW(trig_async_enable); > > ... > >> +static DEVICE_ATTR_RW(trig_flag_ts_enable); > > ... > >> +static DEVICE_ATTR_RW(trig_freq_enable); > > ... >> +static DEVICE_ATTR_RW(freq_ts_enable); > > These attribute are boolean and looks like we could save some space on > code by using dev_ext_attribute. > see tpdm_simple_dataset_rw()/tpdm_simple_dataset_ro() . You could > > #define TPDA_TRIG_ASYNC        0 > #define TPDA_TRIG_FLAG_TS     1 > #define TPDA_TRIG_FREQ        2 > > > tpda_trig_sysfs_show/store() > >  bool *ptr; >  switch (eattr->var) { >  case TPDA_TRIG_ASYNC: >     ptr = &drvdata->trig_async; >     break; >  case TPDA_TRIG_FLAG_TS: >     ptr = &drvdata->trig_flag_ts; >     break; > ... > >  } > Will wrap in tpda_trig_sysfs_show/store(). > > >> + >> +static ssize_t global_flush_req_show(struct device *dev, >> +                     struct device_attribute *attr, >> +                     char *buf) >> +{ >> +    struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); >> +    unsigned long val; >> + >> +    if (!drvdata->csdev->refcnt) >> +        return -EINVAL; >> + >> +    guard(spinlock)(&drvdata->spinlock); >> +    CS_UNLOCK(drvdata->base); >> +    val = readl_relaxed(drvdata->base + TPDA_CR); >> +    CS_LOCK(drvdata->base); >> +    /* Only read value for bit 0 */ >> +    val &= BIT(0); >> + >> +    return sysfs_emit(buf, "%lu\n", val); >> +} >> + >> +static ssize_t global_flush_req_store(struct device *dev, >> +                      struct device_attribute *attr, >> +                      const char *buf, >> +                      size_t size) >> +{ >> +    struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); >> +    unsigned long val; >> + >> +    if (kstrtoul(buf, 0, &val)) >> +        return -EINVAL; >> + >> +    if (!drvdata->csdev->refcnt || !val) >> +        return -EINVAL; >> + >> +    guard(spinlock)(&drvdata->spinlock); >> +    CS_UNLOCK(drvdata->base); >> +    val = readl_relaxed(drvdata->base + TPDA_CR); >> +    /* Only set bit 0 */ >> +    val |= BIT(0); > > What is BIT 0 ? Please document it will document it. Bit0 is Global (all ports) flush request bit. Set 1 means a flush request is made for all ports. > >> +    writel_relaxed(val, drvdata->base + TPDA_CR); >> +    CS_LOCK(drvdata->base); >> + >> +    return size; >> +} >> +static DEVICE_ATTR_RW(global_flush_req); > > > >> + >> +static ssize_t cmbchan_mode_show(struct device *dev, >> +                 struct device_attribute *attr, >> +                 char *buf) >> +{ >> +    struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); >> + >> +    return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->cmbchan_mode); >> +} >> + >> +static ssize_t cmbchan_mode_store(struct device *dev, >> +                  struct device_attribute *attr, >> +                  const char *buf, >> +                  size_t size) >> +{ >> +    struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); >> +    unsigned long val; >> + >> +    if (kstrtoul(buf, 0, &val)) >> +        return -EINVAL; >> + >> +    guard(spinlock)(&drvdata->spinlock); >> +    drvdata->cmbchan_mode = !!val; >> + >> +    return size; >> +} >> +static DEVICE_ATTR_RW(cmbchan_mode); > > Even this could go to the dev_ext_attribute magic and reuse a single > show/store. Got it. > >> + >> +static struct attribute *tpda_attrs[] = { >> +    &dev_attr_trig_async_enable.attr, >> +    &dev_attr_trig_flag_ts_enable.attr, >> +    &dev_attr_trig_freq_enable.attr, >> +    &dev_attr_freq_ts_enable.attr, >> +    &dev_attr_global_flush_req.attr, >> +    &dev_attr_cmbchan_mode.attr, >> +    NULL, >> +}; > >> diff --git a/drivers/hwtracing/coresight/coresight-tpda.h b/drivers/ >> hwtracing/coresight/coresight-tpda.h >> index c6af3d2da3ef..0be625fb52fd 100644 >> --- a/drivers/hwtracing/coresight/coresight-tpda.h >> +++ b/drivers/hwtracing/coresight/coresight-tpda.h >> @@ -1,6 +1,6 @@ >>   /* SPDX-License-Identifier: GPL-2.0 */ >>   /* >> - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights >> reserved. >> + * Copyright (c) 2023,2025 Qualcomm Innovation Center, Inc. All >> rights reserved. >>    */ >>   #ifndef _CORESIGHT_CORESIGHT_TPDA_H >> @@ -8,6 +8,19 @@ >>   #define TPDA_CR            (0x000) >>   #define TPDA_Pn_CR(n)        (0x004 + (n * 4)) >> +#define TPDA_FPID_CR        (0x084) >> + >> +/* Cross trigger FREQ packets timestamp bit */ >> +#define TPDA_CR_FREQTS        BIT(2) >> +/* Cross trigger FREQ packet request bit */ >> +#define TPDA_CR_FRIE        BIT(3) >> +/* Cross trigger FLAG packet request interface bit */ >> +#define TPDA_CR_FLRIE        BIT(4) >> +/* Cross trigger synchronization bit */ >> +#define TPDA_CR_SRIE        BIT(5) >> +/* Packetize CMB/MCMB traffic bit */ >> +#define TPDA_CR_CMBCHANMODE    BIT(20) >> + > > Why are these not clubbed with the other TPDA_CR_ defintions ? I should put this bit after: /* Bits 6 ~ 12 is for atid value */ #define TPDA_CR_ATID GENMASK(12, 6) +/* Bits 13 ~ 19 is for mid value */ +#define TPDA_CR_MID GENMASK(19, 13) MID here is the master ID which is used to identify the TPDA device itself in received packets when multiple tpda devices are enabled. Thanks, Jie > >>   /* Aggregator port enable bit */ >>   #define TPDA_Pn_CR_ENA        BIT(0) >>   /* Aggregator port CMB data set element size bit */ >> @@ -19,6 +32,8 @@ >>   /* Bits 6 ~ 12 is for atid value */ >>   #define TPDA_CR_ATID        GENMASK(12, 6) >> +/* Bits 13 ~ 19 is for mid value */ >> +#define TPDA_CR_MID        GENMASK(19, 13) >>   /** >>    * struct tpda_drvdata - specifics associated to an TPDA component >> @@ -29,6 +44,11 @@ >>    * @enable:     enable status of the component. >>    * @dsb_esize   Record the DSB element size. >>    * @cmb_esize   Record the CMB element size. >> + * @trig_async:    Enable/disable cross trigger synchronization >> sequence interface. >> + * @trig_flag_ts: Enable/disable cross trigger FLAG packet request >> interface. >> + * @trig_freq:    Enable/disable cross trigger FREQ packet request >> interface. >> + * @freq_ts:    Enable/disable the timestamp for all FREQ packets. >> + * @cmbchan_mode: Configure the CMB/MCMB channel mode. >>    */ >>   struct tpda_drvdata { >>       void __iomem        *base; >> @@ -38,6 +58,11 @@ struct tpda_drvdata { >>       u8            atid; >>       u32            dsb_esize; >>       u32            cmb_esize; >> +    bool            trig_async; >> +    bool            trig_flag_ts; >> +    bool            trig_freq; >> +    bool            freq_ts; >> +    bool            cmbchan_mode; >>   }; >>   #endif  /* _CORESIGHT_CORESIGHT_TPDA_H */ > > Suzuki >