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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b734fad456bsm1345508066b.21.2025.11.18.02.23.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 18 Nov 2025 02:23:46 -0800 (PST) Message-ID: Date: Tue, 18 Nov 2025 11:23:43 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 2/2] arm64: dts: qcom: Add PCIe3 and PCIe5 regulators for HAMAO-IOT-EVK board To: Ziyue Zhang , Dmitry Baryshkov Cc: andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, jingoohan1@gmail.com, mani@kernel.org, lpieralisi@kernel.org, kwilczynski@kernel.org, bhelgaas@google.com, johan+linaro@kernel.org, vkoul@kernel.org, kishon@kernel.org, neil.armstrong@linaro.org, abel.vesa@linaro.org, kw@linux.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, qiang.yu@oss.qualcomm.com, krishna.chundru@oss.qualcomm.com, quic_vbadigan@quicinc.com References: <20251112090316.936187-1-ziyue.zhang@oss.qualcomm.com> <20251112090316.936187-3-ziyue.zhang@oss.qualcomm.com> <12bce4de-9491-4040-991b-529bc916983c@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <12bce4de-9491-4040-991b-529bc916983c@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: GUhXK5_2lIT-Yg5u-2kOWRAmZirViIDP X-Proofpoint-GUID: GUhXK5_2lIT-Yg5u-2kOWRAmZirViIDP X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTE4MDA4MiBTYWx0ZWRfX/B+qgIcNnNJj U7V5pvdeou6He5dP88UnuQmFmLIbxgBeGoQ/VvcA0IVKnfnQXDYhsWGuuufEr1ntQtfTzkAbysy 6D8N0ZAW/YzQDTSaNNPWqrxoFaVCVvv5YPjSavjgokfeWID2R/za/CkDaEdymfRjx/z4SHoEqt/ HuRSfwwMx0MGjO7KtKCgbrsYusAnDRDDahnyf7iwvxCzUgB8VSGe3lsw2gN3gayaLs+s9JYecdx sxtbOgTdlx9RhPUV3y9Sfe4/+RJqop/dHlG3jLsT1QmTIuXM2FekHPQqZKK6nagUIpAO4zh3P3s hXj6QFWea6VArDg3pMrixAMmZqXfl+fNOtJuE9vKxYI/0WGtgCBgexZwgEtzYUJnBW/jna0YhRW 6ISlB9ywuDaYtquLxobLwR8l8TMKtw== X-Authority-Analysis: v=2.4 cv=N/Yk1m9B c=1 sm=1 tr=0 ts=691c4934 cx=c_pps a=oc9J++0uMp73DTRD5QyR2A==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=IK9dZxoMItTNHq3eVUAA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=iYH6xdkBrDN1Jqds4HTS:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-17_04,2025-11-13_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 bulkscore=0 adultscore=0 priorityscore=1501 phishscore=0 impostorscore=0 malwarescore=0 suspectscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511180082 On 11/18/25 11:11 AM, Ziyue Zhang wrote: > > On 11/13/2025 5:16 AM, Dmitry Baryshkov wrote: >> On Wed, Nov 12, 2025 at 05:03:16PM +0800, Ziyue Zhang wrote: >>> HAMAO IoT EVK uses PCIe5 to connect an SDX65 module for WWAN functionality >>> and PCIe3 to connect a SATA controller. These interfaces require multiple >>> voltage rails: PCIe5 needs 3.3V supplied by vreg_wwan, while PCIe3 requires >>> 12V, 3.3V, and 3.3V AUX rails, controlled via PMIC GPIOs. >>> >>> Add the required fixed regulators with related pin configuration, and >>> connect them to the PCIe3 and PCIe5 ports to ensure proper power for the >>> SDX65 module and SATA controller. >>> >>> Signed-off-by: Ziyue Zhang >>> Reviewed-by: Krishna Chaitanya Chundru >>> --- >>>   arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts | 83 ++++++++++++++++++++++ >>>   1 file changed, 83 insertions(+) >>> >>> +&pmc8380_3_gpios { >>> +    pm_sde7_aux_3p3_en: pcie-aux-3p3-default-state { >> What is sde7? Other than that: >> >> >> Reviewed-by: Dmitry Baryshkov >> > Hi Dmitry > > I’m not sure what “sde7” refers to specifically. I saw this name in the It refers to "SD Express" which was connected to that PCIe host on some flavors of the internal boards, and the naming must have stuck.. Konrad