Re: [PATCH v2 0/3] Fix using wrong GPF DVSEC location issue

[Dave Jiang <dave.jiang@intel.com>]

On 3/23/25 2:31 AM, Li Ming wrote:
> During review all new patches in branch cxl/next. I noticed there may be
> a problem in below commit.
> 
> commit a52b6a2c1c99 ("cxl/pci: Support Global Persistent Flush (GPF)")
> 
> There is a new field gpf_dvsec in struct cxl_port to cache GPF DVSEC for
> Port(DVSEC ID 04h) location. When the first EP attaching to a cxl port,
> it will trigger locating GPF DVSEC on the cxl dport which the first EP
> is under, then the location is cached in port->gpf_dvsec. So if another
> EP under another dport is attaching, it will reuse the value of
> port->gpf_dvsec as GPF DVSEC location for this another dport. The
> problem is the cached location may be a wrong location for other dports
> of the port.
> 
> Per Table 8-2 in CXL r3.2 section 8.1.1 and CXL r3.2 section 8.1.6, Each
> CXL Downstream switch ports and CXL root ports have their own GPF DVSEC
> for Port(DVSEC ID 04h). So my understanding is that CXL subsystem should
> locate GPF DVSEC for Port for each dport rather than using the cached
> location in CXL port.

Applied to cxl/fixes for 6.15-rc

> 
> base-commit: 3b5d43245f0a56390baaa670e1b6d898772266b3 cxl/next
> 
> v2:
> - Drop RFC tag.
> - Add Fixes tag to patch #1.
> - Pickup reviews.
> - Add tested by Davidlohr.
> - Adjust the changelog of patch #2.(Davidlohr)
> - Fix typo issue in patch #2.(Davidlohr)
> 
> Li Ming (3):
>   cxl/core: Fix caching dport GPF DVSEC issue
>   cxl/pci: Update Port GPF timeout only when the first EP attaching
>   cxl/pci: Drop the parameter is_port of cxl_gpf_get_dvsec()
> 
>  drivers/cxl/core/core.h |  2 +-
>  drivers/cxl/core/pci.c  | 30 +++++++++++++++++-------------
>  drivers/cxl/core/port.c |  2 +-
>  drivers/cxl/cxl.h       |  6 +++---
>  drivers/cxl/pmem.c      |  2 +-
>  5 files changed, 23 insertions(+), 19 deletions(-)
>