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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0f012229sm525618566b.133.2024.12.23.07.02.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 23 Dec 2024 07:02:17 -0800 (PST) Message-ID: Date: Mon, 23 Dec 2024 16:02:15 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 3/7] drm/msm: adreno: dynamically generate GMU bw table To: Neil Armstrong , Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Simona Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org References: <20241217-topic-sm8x50-gpu-bw-vote-v6-0-1adaf97e7310@linaro.org> <20241217-topic-sm8x50-gpu-bw-vote-v6-3-1adaf97e7310@linaro.org> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20241217-topic-sm8x50-gpu-bw-vote-v6-3-1adaf97e7310@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: IaTwxAbVZwPRm3Ozd8dSLXf6Z01lK_dm X-Proofpoint-ORIG-GUID: IaTwxAbVZwPRm3Ozd8dSLXf6Z01lK_dm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 priorityscore=1501 mlxscore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 malwarescore=0 spamscore=0 bulkscore=0 suspectscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412230135 On 17.12.2024 3:51 PM, Neil Armstrong wrote: > The Adreno GPU Management Unit (GMU) can also scale the ddr > bandwidth along the frequency and power domain level, but for > now we statically fill the bw_table with values from the > downstream driver. > > Only the first entry is used, which is a disable vote, so we > currently rely on scaling via the linux interconnect paths. > > Let's dynamically generate the bw_table with the vote values > previously calculated from the OPPs. > > Those entries will then be used by the GMU when passing the > appropriate bandwidth level while voting for a gpu frequency. > > Signed-off-by: Neil Armstrong > --- [...] > + /* > + * These are the CX (CNOC) votes - these are used by the GMU > + * The 'CN0' BCM is used on all targets, and votes are basically > + * 'off' and 'on' states with first bit to enable the path. > + */ > + > + msg->cnoc_cmds_addrs[0] = cmd_db_read_addr("CN0"); > + msg->cnoc_cmds_num = 1; > + > + msg->cnoc_cmds_data[0][0] = BCM_TCS_CMD(true, false, 0, 0); > + msg->cnoc_cmds_data[1][0] = BCM_TCS_CMD(true, true, 0, BIT(0)); > + > + /* Compute the wait bitmask with each BCM having the commit bit */ > + msg->cnoc_wait_bitmask = 0; > + for (j = 0; j < msg->cnoc_cmds_num; j++) > + if (msg->cnoc_cmds_data[0][j] & BCM_TCS_CMD_COMMIT_MASK) > + msg->cnoc_wait_bitmask |= BIT(j); Still very much not a fan of this. I think this would be equally telling: /* Always flush on/off commands */ msg->cnoc_wait_bitmask = BIT(0); with or without that: Reviewed-by: Konrad Dybcio Konrad