Re: [PATCH] platform: finally disallow IRQ0 in platform_get_irq() and its ilk

[Sergey Shtylyov <s.shtylyov@omp.ru>]

Hello!

On 11/26/21 7:20 PM, Greg Kroah-Hartman wrote:

>> The commit a85a6c86c25b ("driver core: platform: Clarify that IRQ 0 is
>> invalid") only calls WARN() when IRQ0 is about to be returned, however
>> using IRQ0 is considered invalid (according to Linus) outside the arch/
>> code where it's used by the i8253 drivers. Many driver subsystems treat
>> 0 specially (e.g. as an indication of the polling mode by libata), so
>> the users of platform_get_irq[_byname]() in them would have to filter
>> out IRQ0 explicitly and this (quite obviously) doesn't scale...
>> Let's finally get this straight and return -EINVAL instead of IRQ0!
>>
>> Fixes: a85a6c86c25b ("driver core: platform: Clarify that IRQ 0 is invalid")
>> Signed-off-by: Sergey Shtylyov <s.shtylyov@omp.ru>
>>
>> ---
>> The patch is against the 'driver-core-linus' branch of Greg Kroah-Hartman's
>> 'driver-core.git' repo.
>>
>>  drivers/base/platform.c |    6 ++++--
>>  1 file changed, 4 insertions(+), 2 deletions(-)
>>
>> Index: driver-core/drivers/base/platform.c
>> ===================================================================
>> --- driver-core.orig/drivers/base/platform.c
>> +++ driver-core/drivers/base/platform.c
>> @@ -231,7 +231,8 @@ int platform_get_irq_optional(struct pla
>>  out_not_found:
>>  	ret = -ENXIO;
>>  out:
>> -	WARN(ret == 0, "0 is an invalid IRQ number\n");
>> +	if (WARN(!ret, "0 is an invalid IRQ number\n"))
>> +		return -EINVAL;
> 
> You need to get approval from the interrrupt developers for this type of
> change, as it is a change and might break existing platforms, right?

   Well, that's always possible... :-)

   I do remember we had issues with the serial driver on the Alchemy MIPS SoCs
back in the 2.6.1x time frame: UART0 used IRQ0 there and the serial driver treated
0 as an indication of the polling mode, IIRC... Now Alchemies have the SoC IRQ0
mapped to the Linux IRQ8, so this is not a problem anymore (the 1st 8 IRQs are
mapped to the MIPS CPU IRQs and IRQ0 isn't even used)...

> thanks,
> 
> greg k-h

MBR, Sergey