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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: ZhWvIK3aWQR7XFMxHkEOtUGL452YQ1KcXtd0gaaC2G/Ky2A4618Agux0WAorQ9aaHWdQCslpw0DaHnS+GuNPgFaA/GJLPCrBExEDLY+2hiOpOlcWlFt+3mjRczcdleGp6Qd40w5VFVtFbjYqh1E5Tkpy+KoCGeB3KKJaFpjcMQCLtqVI+/xyh5ZKwMsbUUR6hmL+K44p/KkCDyU99x49N0uyevzQbN4KXkxkTJUxYsmP802BtLgRrTsXWvYv4sN7L9DAXJ8bk6lFTTEqpRy/w5mZ1Aly4KwGDfChZGcbF3yN7pWsdZ4NhIQWLGHbJCVUw0vfA6PG9GfPZvYSud2tf03YNqO22e5elV7YupQ59F2nQ0x7Pb20Y/QyTQnSbB+vQ5p1EDql4wTnoLMq5tDiDvLcpbnXC8q6FPvvbF56z15pFCcjVn+aAoAk1PQPtHd4 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Mar 2026 09:41:00.9450 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d0f241b9-f6d3-4361-dfae-08de7b647a2f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002636C.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7827 Hi Andrew, On 11-02-2026 06:23, Andrew Cooper wrote: >> Here is the newly published FRED virtualization spec by AMD for reference: >> >> https://docs.amd.com/v/u/en-US/69191-PUB >> >> Please feel free to share any feedback or questions. > > > FYI, there is a fun behaviour captured in the sentence: > > "If FRED virtualization is enabled, NMI virtualization must be enabled > in order to properly handle guest NMIs" > > i.e. hypervisors need to make sure not run the guest with FRED && > !vNMI.  AIUI, there's no ERETUx intercept similar to the IRET intercept > with with to emulate NMI window tracking in !vNMI mode. Thanks for letting me know about this. Seems like a legitimate consistency check. I'll try to integrate it. > > I requested that this become a VMRUN consistency check, but was > declined.  I've asked that at least the wording change to "undefined > behaviour" so something sane can be done for the nested case where L1 > tries to do something daft. > > > There are two other issues which are going to be adjusted.  One is the > consistency check concerning SS.DPL==3 && INTR_SHADOW==0 (not a valid > restriction in later drafts of the spec), and one is "On an intercepted > #DB, EXITINFO2 has DR6 register value."  Both do/will (not sure which) > behave like Intel, rather than as currently documented. Can you tell under which conditions does the #DB issue may arise? > > ~Andrew - Shivansh