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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b97f142a785sm426601566b.14.2026.03.19.03.04.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 19 Mar 2026 03:04:45 -0700 (PDT) Message-ID: Date: Thu, 19 Mar 2026 11:04:42 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 3/3] drm/msm/dpu: fix video mode DSC INTF timing width for non 8 bit panels To: Neil Armstrong , Alexander Koskovich , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org References: <20260318-dsi-rgb101010-support-v2-0-698b7612eaeb@pm.me> <20260318-dsi-rgb101010-support-v2-3-698b7612eaeb@pm.me> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: 2SSwIHZzF5oDWLB9wSP8t0G-6KWkz_-J X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzE5MDA3OSBTYWx0ZWRfX6hczv15lQaQ2 o7YeS2uo9VEQyCbENH6q/iydSIgu98nLA0xCFbfcHLAc0boXsnJ9W+aw1rColdWant3JwoXWeuw dnxlc0gATQkDkYJbMVURyXXnZRTWC8ICf9QURJEEL7CxsZqJPfDOlszu1zNV82Om0aQDdHPOm1Q 2uGAm4HY92QV4PgK5SUEjbCsKoY8Exn/hqbXNUMdjMWq/CGJpvKhkWMaT17Bd8OpW0fbRow3B3l 7A63jVAeBlhAe9gN7PKskrdCYECVBRkuWfDKn7Fu2Bk92u8zvNArVbUMceGGP3HYsdI4vxevI83 HWDFcx+/COjo4jFa4HHPCxj3auC+GHa+wQ/VHSpE7RamD2UjsSKJkAnrv8/JoEtmNns+jiMlXP0 7QnzG0113f/SPbS29GHfB+QGBFl1BaRaU+iSO/69086Kb2XSl2GXKFVHvkF9d0rtYxbq8ByBYiZ XzWbGR3jDg7jvDh8JTA== X-Proofpoint-GUID: 2SSwIHZzF5oDWLB9wSP8t0G-6KWkz_-J X-Authority-Analysis: v=2.4 cv=PtCergM3 c=1 sm=1 tr=0 ts=69bbca3f cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=FH03U6bJQyAcg50I1OgA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=dawVfQjAaf238kedN5IG:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-19_01,2026-03-17_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 clxscore=1015 priorityscore=1501 bulkscore=0 lowpriorityscore=0 malwarescore=0 spamscore=0 adultscore=0 suspectscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603190079 On 3/19/26 9:34 AM, Neil Armstrong wrote: > On 3/19/26 05:00, Alexander Koskovich wrote: >> Using bits_per_component * 3 as the divisor for the compressed INTF >> timing width produces constant FIFO errors for panels such as the BOE >> BF068MWM-TD0 which is a 10 bit panel. >> >> The downstream driver calculates the compressed timing width by >> dividing the total compressed bytes per line by 3 which does not depend >> on bits_per_component. Switch the divisor to 24 to match downstream. >> >> Signed-off-by: Alexander Koskovich >> --- >>   drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 12 +++++++----- >>   1 file changed, 7 insertions(+), 5 deletions(-) >> >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c >> index 0ba777bda253..9b046a0e77aa 100644 >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c >> @@ -122,19 +122,21 @@ static void drm_mode_to_intf_timing_params( >>       } >>         /* >> -     * for DSI, if compression is enabled, then divide the horizonal active >> -     * timing parameters by compression ratio. bits of 3 components(R/G/B) >> -     * is compressed into bits of 1 pixel. >> +     * For DSI, if DSC is enabled, use a fixed divisor of 24 rather than >> +     * bits_per_component * 3 when calculating the compressed timing width. >> +     * >> +     * This matches the downstream driver and is required for panels with >> +     * bits_per_component != 8. >>        */ >>       if (phys_enc->hw_intf->cap->type != INTF_DP && timing->compression_en) { >>           struct drm_dsc_config *dsc = >>                  dpu_encoder_get_dsc_config(phys_enc->parent); >> + >>           /* >>            * TODO: replace drm_dsc_get_bpp_int with logic to handle >>            * fractional part if there is fraction >>            */ >> -        timing->width = timing->width * drm_dsc_get_bpp_int(dsc) / >> -                (dsc->bits_per_component * 3); >> +        timing->width = timing->width * drm_dsc_get_bpp_int(dsc) / 24; > > > > @bits_per_component: Bits per component to code (8/10/12) <= how the DSC pixels are encoded in the stream > @bits_per_pixel: Target bits per pixel with 4 fractional bits, bits_per_pixel << 4 <= the target display pixels > > - bits_per_component is the transport width > - bits_per_pixel is the display width > - 3 is the DSC compression ratio > > So for a RGB101010 DSC display bits_per_pixel should be 10 << 4 > > But here you say bits_per_component should be 8 ? can you share the downstream config of your panel ? > > Are you sure about the bits_per_component & bits_per_pixel values you set in the dsc parameters ? The computer tells me that if widebus=off, regardless of the compression ratio and pixel depth before compression, 24 bits of compressed data are transferred per pclk, and then you can transfer 1/2/4 slices per xfer (As a note, the DSC compression ratio isn't fixed) This also impacts the byte/pixel clock calculations (but dsi_host.c seems to have taken care of that) Maybe Dmitry knows something more.. Konrad