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([2a01:e0a:982:cbb0:bf4e:5758:59ef:deb8]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436e2e89df1sm80587885e9.27.2025.01.10.01.49.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 10 Jan 2025 01:49:52 -0800 (PST) Message-ID: Date: Fri, 10 Jan 2025 10:49:50 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Reply-To: neil.armstrong@linaro.org Subject: Re: [PATCH] arm64: dts: qcom: add missing cache node for cpu1 From: Neil Armstrong To: Konrad Dybcio , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250109-topic-sm8650-cpu1-missing-cache-v1-1-0e85148a48a8@linaro.org> <549d15ae-34db-497c-89d7-c9b9c18d8681@oss.qualcomm.com> <99747e37-1288-4d70-a678-0a73bb4c3b3f@linaro.org> Content-Language: en-US, fr Autocrypt: addr=neil.armstrong@linaro.org; keydata= xsBNBE1ZBs8BCAD78xVLsXPwV/2qQx2FaO/7mhWL0Qodw8UcQJnkrWmgTFRobtTWxuRx8WWP GTjuhvbleoQ5Cxjr+v+1ARGCH46MxFP5DwauzPekwJUD5QKZlaw/bURTLmS2id5wWi3lqVH4 BVF2WzvGyyeV1o4RTCYDnZ9VLLylJ9bneEaIs/7cjCEbipGGFlfIML3sfqnIvMAxIMZrvcl9 qPV2k+KQ7q+aXavU5W+yLNn7QtXUB530Zlk/d2ETgzQ5FLYYnUDAaRl+8JUTjc0CNOTpCeik 80TZcE6f8M76Xa6yU8VcNko94Ck7iB4vj70q76P/J7kt98hklrr85/3NU3oti3nrIHmHABEB AAHNKk5laWwgQXJtc3Ryb25nIDxuZWlsLmFybXN0cm9uZ0BsaW5hcm8ub3JnPsLAkQQTAQoA OwIbIwULCQgHAwUVCgkICwUWAgMBAAIeAQIXgBYhBInsPQWERiF0UPIoSBaat7Gkz/iuBQJk Q5wSAhkBAAoJEBaat7Gkz/iuyhMIANiD94qDtUTJRfEW6GwXmtKWwl/mvqQtaTtZID2dos04 YqBbshiJbejgVJjy+HODcNUIKBB3PSLaln4ltdsV73SBcwUNdzebfKspAQunCM22Mn6FBIxQ GizsMLcP/0FX4en9NaKGfK6ZdKK6kN1GR9YffMJd2P08EO8mHowmSRe/ExAODhAs9W7XXExw UNCY4pVJyRPpEhv373vvff60bHxc1k/FF9WaPscMt7hlkbFLUs85kHtQAmr8pV5Hy9ezsSRa GzJmiVclkPc2BY592IGBXRDQ38urXeM4nfhhvqA50b/nAEXc6FzqgXqDkEIwR66/Gbp0t3+r yQzpKRyQif3OwE0ETVkGzwEIALyKDN/OGURaHBVzwjgYq+ZtifvekdrSNl8TIDH8g1xicBYp QTbPn6bbSZbdvfeQPNCcD4/EhXZuhQXMcoJsQQQnO4vwVULmPGgtGf8PVc7dxKOeta+qUh6+ SRh3vIcAUFHDT3f/Zdspz+e2E0hPV2hiSvICLk11qO6cyJE13zeNFoeY3ggrKY+IzbFomIZY 4yG6xI99NIPEVE9lNBXBKIlewIyVlkOaYvJWSV+p5gdJXOvScNN1epm5YHmf9aE2ZjnqZGoM Mtsyw18YoX9BqMFInxqYQQ3j/HpVgTSvmo5ea5qQDDUaCsaTf8UeDcwYOtgI8iL4oHcsGtUX oUk33HEAEQEAAcLAXwQYAQIACQUCTVkGzwIbDAAKCRAWmrexpM/4rrXiB/sGbkQ6itMrAIfn M7IbRuiSZS1unlySUVYu3SD6YBYnNi3G5EpbwfBNuT3H8//rVvtOFK4OD8cRYkxXRQmTvqa3 3eDIHu/zr1HMKErm+2SD6PO9umRef8V82o2oaCLvf4WeIssFjwB0b6a12opuRP7yo3E3gTCS KmbUuLv1CtxKQF+fUV1cVaTPMyT25Od+RC1K+iOR0F54oUJvJeq7fUzbn/KdlhA8XPGzwGRy 4zcsPWvwnXgfe5tk680fEKZVwOZKIEuJC3v+/yZpQzDvGYJvbyix0lHnrCzq43WefRHI5XTT QbM0WUIBIcGmq38+OgUsMYu4NzLu7uZFAcmp6h8g Organization: Linaro In-Reply-To: <99747e37-1288-4d70-a678-0a73bb4c3b3f@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 10/01/2025 10:44, Neil Armstrong wrote: > On 09/01/2025 19:30, Konrad Dybcio wrote: >> On 9.01.2025 4:24 PM, Neil Armstrong wrote: >>> Add the missing l2-cache node for the cpu1 >>> >>> Fixes: 20eb2057b3e4 ("arm64: dts: qcom: sm8650: change labels to lower-case") >>> Fixes: d2350377997f ("arm64: dts: qcom: add initial SM8650 dtsi") >>> Signed-off-by: Neil Armstrong >>> --- >> >> subject: missing `sm8650:` > > Damn > >> >>>   arch/arm64/boot/dts/qcom/sm8650.dtsi | 7 +++++++ >>>   1 file changed, 7 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi >>> index 86684cb9a9325618ddb74458621cf4bbdc1cc0d1..832f3a2c400e8348847bc24b27397e2a0dc08db8 100644 >>> --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi >>> +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi >>> @@ -119,6 +119,13 @@ cpu1: cpu@100 { >>>               qcom,freq-domain = <&cpufreq_hw 0>; >>>               #cooling-cells = <2>; >>> + >>> +            l2_100: l2-cache { >>> +                compatible = "cache"; >>> +                cache-level = <2>; >>> +                cache-unified; >>> +                next-level-cache = <&l3_0>; >>> +            }; >>>           }; >> >> You likely wanted to hook up this new node to CPU1 as well. >> >> Reading some Arm docs [1], it seems like with A520 specifically, both shared >> and unique cache slices are permitted, depending on whether they're >> implemented as single- or dual-core complexes (not to be confused with >> multi-threading) >> >> [2] suggests CA720s always have their own cache pools >> >> In 8650's case, the slowest cluster has a shared L2 cache, whereas cores 2-7 >> have their own pools, so this patch is incorrect. > > Damn you're right, so the cpu1 cache should be linked to the cpu0 cache somehow Well, stupid me, it's already done... sorry for the noise and thx for your review Neil > > Thanks, > Neil > >> >> Konrad >> >> [1] https://developer.arm.com/documentation/102517/0004/The-Cortex-A520--core/Cortex-A520--core-configuration-options >> [2] https://developer.arm.com/documentation/102530/0001/L2-memory-system >