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charset=UTF-8 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=LL1mQIW9 c=1 sm=1 tr=0 ts=687ffd22 cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=4dphQItTPUswyQvINXrzgA==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=q7gkdMK14rNBkceAJS4A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=_Vgx9l1VpLgwpw_dHYaR:22 X-Proofpoint-GUID: C52E8jOGGVVq6KS6uvo758MVZyNjtdxS X-Proofpoint-ORIG-GUID: C52E8jOGGVVq6KS6uvo758MVZyNjtdxS X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzIyMDE4MiBTYWx0ZWRfXxeehZQSyDKbn X+wZqsvKJTADYEciA7tuyaSGrgnR19GRujYha3LGSVGzR8HW+zbf9bkzLr97/4mZw9GTrVyrBl7 uufqZZC1bqVpYTUFrulKa3odv+v8VcD/FCcPiG3JNZin8LC/kV5KbNJ666czw5Kary5l+mnN7qN XcOYiMxFQ04Mv5i30wSuwqY4NWRovMAdTzA0E7YukyJi9mhyz3qrNwLej88R7x2b53vhPCN8rom Lph5f1VBjgs0TzrIb2RZZBZo/JzYJtTbBpIBBoS2oKELO1/nOpVc/LSvO6BrBu6uP1SA6f6M7eg UfY2/jaEf4tA2pH/A1XJB5eByj7vu5RRtY+aaMjkN+Q4y/r5l9Z79P4KnzODaOPndcKOMg3nTze tl5Noe7Lcj6tLNXoAUItmLsUQoJkApZcF5dIRW6sODuSkVuXKRmmtA39Y4G7OkjgTCupMt95 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-22_03,2025-07-22_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxlogscore=999 clxscore=1015 mlxscore=0 adultscore=0 suspectscore=0 spamscore=0 malwarescore=0 impostorscore=0 bulkscore=0 lowpriorityscore=0 phishscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507220182 On 7/22/2025 10:56 PM, Rob Clark wrote: > On Tue, Jul 22, 2025 at 6:33 AM Dmitry Baryshkov > wrote: >> >> On Sun, Jul 20, 2025 at 05:46:06PM +0530, Akhil P Oommen wrote: >>> Since the PDC resides out of the GPU subsystem and cannot be reset in >>> case it enters bad state, utmost care must be taken to trigger the PDC >>> wake/sleep routines in the correct order. >>> >>> The PDC wake sequence can be exercised only after a PDC sleep sequence. >>> Additionally, GMU firmware should initialize a few registers before the >>> KMD can trigger a PDC sleep sequence. So PDC sleep can't be done if the >> >> s/KMD/the driver/ > > IMHO for gpu things "KMD" makes sense, to differentiate between kernel > and user mode (UMD).. this is perhaps different from other areas where > there isn't a userspace component to the driver stack Ack > > BR, > -R > >>> GMU firmware has not initialized. Track these dependencies using a new >>> status variable and trigger PDC sleep/wake sequences appropriately. >> >> Again, it looks like there should be a Fixes tag here. Ack. I guess it is not a bad idea to backport this one too. >> >>> >>> Signed-off-by: Akhil P Oommen >>> --- >>> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 30 +++++++++++++++++++----------- >>> drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 6 ++++++ >>> 2 files changed, 25 insertions(+), 11 deletions(-) >>> >>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c >>> index 3bebb6dd7059782ceca29f2efd2acee24d3fc930..4d6c70735e0892ed87d6a68d64f24bda844e5e16 100644 >>> --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c >>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c >>> @@ -279,6 +279,8 @@ static int a6xx_gmu_start(struct a6xx_gmu *gmu) >>> if (ret) >>> DRM_DEV_ERROR(gmu->dev, "GMU firmware initialization timed out\n"); >>> >>> + set_bit(GMU_STATUS_FW_START, &gmu->status); >>> + >>> return ret; >>> } >>> >>> @@ -528,6 +530,9 @@ static int a6xx_rpmh_start(struct a6xx_gmu *gmu) >>> int ret; >>> u32 val; >>> >>> + if (!test_and_clear_bit(GMU_STATUS_PDC_SLEEP, &gmu->status)) >>> + return 0; >>> + >>> gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, BIT(1)); >>> >>> ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_RSCC_CONTROL_ACK, val, >>> @@ -555,6 +560,11 @@ static void a6xx_rpmh_stop(struct a6xx_gmu *gmu) >>> int ret; >>> u32 val; >>> >>> + if (test_and_clear_bit(GMU_STATUS_FW_START, &gmu->status)) >>> + return; >>> + >>> + /* TODO: should we skip if IFPC is not enabled */ >> >> Is this a question or a statement? It was a reminder to myself which I forgot to revisit later. Will addresss this in the next revision. -Akhil. >> >>> + >>> gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1); >>> >>> ret = gmu_poll_timeout_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, >>> @@ -563,6 +573,8 @@ static void a6xx_rpmh_stop(struct a6xx_gmu *gmu) >>> DRM_DEV_ERROR(gmu->dev, "Unable to power off the GPU RSC\n"); >>> >>> gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0); >>> + >>> + set_bit(GMU_STATUS_PDC_SLEEP, &gmu->status); >>> } >>> >>> static inline void pdc_write(void __iomem *ptr, u32 offset, u32 value) >>> @@ -691,8 +703,6 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu) >>> /* ensure no writes happen before the uCode is fully written */ >>> wmb(); >>> >>> - a6xx_rpmh_stop(gmu); >>> - >>> err: >>> if (!IS_ERR_OR_NULL(pdcptr)) >>> iounmap(pdcptr); >>> @@ -852,19 +862,15 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) >>> else >>> gmu_write(gmu, REG_A6XX_GMU_GENERAL_7, 1); >>> >>> - if (state == GMU_WARM_BOOT) { >>> - ret = a6xx_rpmh_start(gmu); >>> - if (ret) >>> - return ret; >>> - } else { >>> + ret = a6xx_rpmh_start(gmu); >>> + if (ret) >>> + return ret; >>> + >>> + if (state == GMU_COLD_BOOT) { >>> if (WARN(!adreno_gpu->fw[ADRENO_FW_GMU], >>> "GMU firmware is not loaded\n")) >>> return -ENOENT; >>> >>> - ret = a6xx_rpmh_start(gmu); >>> - if (ret) >>> - return ret; >>> - >>> ret = a6xx_gmu_fw_load(gmu); >>> if (ret) >>> return ret; >>> @@ -1046,6 +1052,8 @@ static void a6xx_gmu_force_off(struct a6xx_gmu *gmu) >>> >>> /* Reset GPU core blocks */ >>> a6xx_gpu_sw_reset(gpu, true); >>> + >>> + a6xx_rpmh_stop(gmu); >>> } >>> >>> static void a6xx_gmu_set_initial_freq(struct msm_gpu *gpu, struct a6xx_gmu *gmu) >>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h >>> index b2d4489b40249b1916ab4a42c89e3f4bdc5c4af9..034f1b4e5a3fb9cd601bfbe6d06d64e5ace3b6e7 100644 >>> --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h >>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h >>> @@ -117,6 +117,12 @@ struct a6xx_gmu { >>> >>> struct qmp *qmp; >>> struct a6xx_hfi_msg_bw_table *bw_table; >>> + >>> +/* To check if we can trigger sleep seq at PDC. Cleared in a6xx_rpmh_stop() */ >>> +#define GMU_STATUS_FW_START 0 >>> +/* To track if PDC sleep seq was done */ >>> +#define GMU_STATUS_PDC_SLEEP 1 >>> + unsigned long status; >>> }; >>> >>> static inline u32 gmu_read(struct a6xx_gmu *gmu, u32 offset) >>> >>> -- >>> 2.50.1 >>> >> >> -- >> With best wishes >> Dmitry