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([2800:a4:806:ef00:2f77:7097:372d:6d14]) by smtp.gmail.com with ESMTPSA id 956f58d0204a3-67c589f065dsm3149000d50.16.2026.11.10.15.52.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 10 Nov 2026 15:52:12 -0800 (PST) Message-ID: Date: Tue, 10 Nov 2026 23:52:03 +0000 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 3/7] dt-bindings: phy: qcom,sm8150-csi2-phy: Add SM8150 CSI2 PHY To: Vladimir Zapolskiy , Loic Poulain , Robert Foss , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue , Mauro Carvalho Chehab , Bryan O'Donoghue , Bjorn Andersson , Konrad Dybcio , Abel Vesa , Andi Shyti , Vinod Koul , Neil Armstrong , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-phy@lists.infradead.org References: <20261106-sm8150-v7.4-rc1-camss-v3-0-0103e8a0bbcd@andrewgigena.dev> <20261106-sm8150-v7.4-rc1-camss-v3-3-0103e8a0bbcd@andrewgigena.dev> Content-Language: en-US From: Andrew Gigena In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Hi Vladimir, Thanks for the review, replies below. > Please double check if SM8150 CSIPHY v1.1 is capable of C-PHY: The hardware can do combo mode, but the driver only implements D-PHY and returns -EOPNOTSUPP for C-PHY, so the binding stays D-PHY. Would you like it documented as "not yet supported" anyway? > D-PHY combo mode is also supported on the SM8150 CSIPHY apparently, > it shall be reflected in a way that two endpoints could be present. Split mode is described in the binding, but the driver rejects it, so it cannot be used today. Is it fine to keep it out until the driver supports it? > In downstream camcc-sm8150.c, PLL0 is on MX, and PLL0 supplies CSIPHY > clocks. I believe MX shall be added to the list of 'power-domains'. You are right that PLL0 uses the MX corner in camcc, but that corner is internal to the clock controller, not a power domain of the CSIPHY. The PHY only consumes the top GDSC; SM8150 uses legacy GDSCs, while on X1E MX is a real power domain attached by the PHY driver. > Still it would be preferred to get 'vdda-0p9-supply' and > 'vdda-1p2-supply' properties. Renamed in the binding on v4, the driver and the DTS, matching the X1E naming. > In general the change looks good, thank you, but likely it can be > embedded into the scheme for X1E. Clocks, register offset, power domains, lane table and timer all differ, so folding it in would need if/then blocks for almost every property. Would you still prefer that, or is a separate schema acceptable? Best regards, Andrew