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Fri, 17 Nov 2023 05:36:34 GMT Received: from [10.214.66.253] (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Thu, 16 Nov 2023 21:36:29 -0800 Message-ID: Date: Fri, 17 Nov 2023 11:06:26 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/3] iommu/arm-smmu: add ACTLR data and support for SM8550 Content-Language: en-US To: Dmitry Baryshkov CC: Konrad Dybcio , , , , , , , , , , , References: <20231114135654.30475-1-quic_bibekkum@quicinc.com> <20231114135654.30475-3-quic_bibekkum@quicinc.com> <7edad996-f148-42d5-8e72-0334d3b9101f@quicinc.com> <61d2885a-50f9-419f-8473-10308baed493@quicinc.com> From: Bibek Kumar Patro In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: hu5XdWHLnDORm0bOjy4slDoorJfl-3dC X-Proofpoint-ORIG-GUID: hu5XdWHLnDORm0bOjy4slDoorJfl-3dC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-17_03,2023-11-16_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxscore=0 clxscore=1015 phishscore=0 mlxlogscore=835 suspectscore=0 bulkscore=0 adultscore=0 spamscore=0 malwarescore=0 lowpriorityscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311170038 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 11/16/2023 12:21 PM, Dmitry Baryshkov wrote: > On Thu, 16 Nov 2023 at 08:10, Bibek Kumar Patro > wrote: >> >> >> >> On 11/15/2023 10:12 PM, Konrad Dybcio wrote: >>> >>> >>> On 11/15/23 13:49, Bibek Kumar Patro wrote: >>>> >>>> >>>> On 11/15/2023 4:15 PM, Dmitry Baryshkov wrote: >>>>> On Wed, 15 Nov 2023 at 11:51, Bibek Kumar Patro >>>>> wrote: >>>>>> >>>>>> >>>>>> >>>>>> On 11/15/2023 3:08 PM, Dmitry Baryshkov wrote: >>>>>>> On Wed, 15 Nov 2023 at 11:22, Bibek Kumar Patro >>>>>>> wrote: >>>>>>>> >>>>>>>> >>>>>>>> >>>>>>>> On 11/14/2023 7:42 PM, Dmitry Baryshkov wrote: >>>>>>>>> On Tue, 14 Nov 2023 at 15:57, Bibek Kumar Patro >>>>>>>>> wrote: >>>>>>>>>> >>>>>>>>>> Add ACTLR data table for SM8550 along with support for >>>>>>>>>> same including SM8550 specific implementation operations. >>>>>>>>>> >>>>>>>>>> Signed-off-by: Bibek Kumar Patro >>>>>>>>>> --- >>>>>>>>>> drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 92 >>>>>>>>>> +++++++++++++++++++++- >>>>>>>>>> 1 file changed, 88 insertions(+), 4 deletions(-) >>>>>>>>>> >>>>>>>>>> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c >>>>>>>>>> b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c >>>>>>>>>> index 578c662c7c30..0eaf6f2a2e49 100644 >>>>>>>>>> --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c >>>>>>>>>> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c >>>>>>>>>> @@ -25,6 +25,70 @@ struct actlr_data { >>>>>>>>>> u32 actlr; >>>>>>>>>> }; >>>>>>>>>> >>>>>>>>>> +#define PRE_FETCH_1 0 >>>>>>>>>> +#define PRE_FETCH_2 BIT(8) >>>>>>>>>> +#define PRE_FETCH_3 (BIT(9) | BIT(8)) >>>>>>>>> >>>>>>>>> What is the difference between PRE_FETCH_3 and PRE_FETCH_2? And >>>>>>>>> PRE_FETCH_1? Are these real numbers that refer to some amount / >>>>>>>>> count >>>>>>>>> or just dummy names? >>>>>>>>> >>>>>>>> >>>>>>>> No,these are not real numbers, but prefetch settings for a particular >>>>>>>> perfect configuration. >>>>>>> >>>>>>> Then I'd ask for some better names or descriptions. >>>>>>> >>>>>> >>>>>> Noted, PREFETCH_SETTING_n / PREFETCH_OPTION_n sounds like a better name >>>>>> in the following case. Would it be okay to use this name instead? >>>>> >>>>> Not really. >>>>> >>>> >>>> Any suggestion you have in mind, if not this nomenclature? >>> Dmitry's concern seems to be that you provide: >>> >>> PRE_FETCH_1 /* prefetcher with settings preset no. 1 */ >>> PRE_FETCH_2 /* prefetcher with settings preset no. 2 */ >>> PRE_FETCH_3 /* prefetcher with settings preset no. 3 */ >>> >>> whereas it would be both useful and interesting to see what these >>> settings mean, i.e. what differences there are between all of >>> these presets. >>> >> >> Ah, okay got it now from Dimitry and yours' response. >> But we exactly won't be able to reveal what each of these settings >> mean, as this might risk of revealing IP as ACTLR bits are >> implementation defined (except CPRE and CMTLB) which other SoC vendors >> might be using it in different manner(or different purpose) in their >> downstream implementation. >> We can name it like (e.g PREFETCH_DISABLE, PREFETCH_SHALLOW, >> PREFETCH_DEEP) to indicate the behaviour, but won't be exactly >> name/describe it to explain what it does with a particular setting. > > This is already better than 1,2,3. > Acked, will take care of this in next version.