From: Dave Hansen <dave.hansen@intel.com>
To: ludloff@gmail.com, Borislav Petkov <bp@alien8.de>,
"Ahmed S. Darwish" <darwi@linutronix.de>
Cc: Dave Hansen <dave.hansen@linux.intel.com>,
Ingo Molnar <mingo@redhat.com>,
Thomas Gleixner <tglx@linutronix.de>,
Andrew Cooper <andrew.cooper3@citrix.com>,
"H. Peter Anvin" <hpa@zytor.com>,
Sean Christopherson <seanjc@google.com>,
David Woodhouse <dwmw2@infradead.org>,
Peter Zijlstra <peterz@infradead.org>,
Sohil Mehta <sohil.mehta@intel.com>,
John Ogness <john.ogness@linutronix.de>,
x86@kernel.org, x86-cpuid@lists.linux.dev,
LKML <linux-kernel@vger.kernel.org>
Subject: Re: x86 CPUID mutable return values
Date: Mon, 21 Sep 2026 14:32:04 -0700 [thread overview]
Message-ID: <f133c35f-b013-4395-ad1f-53765114d4b9@intel.com> (raw)
In-Reply-To: <CAKSQd8V28WjMcsfh05P5SNfXXvtafBH6fyiyqMzQ9GtU8fQGSA@mail.gmail.com>
On 9/21/26 11:36, Christian Ludloff wrote:
> Q for Intel: is MSR FEATURE_CONFIG 0x13C bit 1 expected
> to affect CPUID 1.ECX.25 and 7.0.ECX.9 and 19.EBX.0/2, or
> just just a subset of them? Also, what about PCLMUL?
Are you looking to document architecture or implementation here?
I poked around on a few pieces of hardware I have within reach and all
of them have the MSR FEATURE_CONFIG lock bit set and the disable bit clear.
# rdmsr -a 0x13C
1
1
1
1
...
In practice, I suspect the AESNI CPUID bits are immutable.
FEATURE_CONFIG's definitions also looks model specific in the spots I
see it in the SDM. They're also not identical, interestingly enough.
Honestly, FEATURE_CONFIG looks more like something that should have been
in the BIOS writers' guide rather than the SDM.
next prev parent reply other threads:[~2026-09-21 21:32 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-21 18:36 Christian Ludloff
2026-09-21 21:32 ` Dave Hansen [this message]
2026-09-22 8:43 ` Christian Ludloff
2026-09-22 15:24 ` Dave Hansen
2026-09-22 18:28 ` Christian Ludloff
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