From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D9C352F7445 for ; Fri, 3 Jul 2026 04:36:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783053396; cv=none; b=Xf+XT9g3TlNEQ+Iu5zadFyPUUM8CeLIDFQwph/g0z5rY2VmpLNlCSRjJYTTgenIwVrwkEJSIjp8vO3kiFGN5+oqGb1B98SzG6R8qKxWQZSIAOr3SdDgvdOIlj2QTRQfPvcoKb4+5BHN2fKduV+o+u8AWzKDsUrO4EXl+qY0V3ms= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783053396; c=relaxed/simple; bh=Huf4PlM1oSkcNi7ICVIfuvMLySVEdvCv0CiezIssnPo=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=mTf5H286qbMwzRCUzis1C5OEar4QE3PGLwhjCIvb/DoCIrEaxhStEwcWr9n2ZAD3iKeaTANqvvQynSnvN51RVwEPI8YUqSxF77iaWkVZCQm8F5kGcP9/jJjLABLJ+Eg9yP85gyPJL2YvS+DllEO5btR4JpEu/NyiZhdWaxAplwU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=QZcCEpXe; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="QZcCEpXe" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 346B91CC4; Thu, 2 Jul 2026 21:36:20 -0700 (PDT) Received: from [10.163.170.216] (unknown [10.163.170.216]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1E5643F905; Thu, 2 Jul 2026 21:36:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1783053384; bh=Huf4PlM1oSkcNi7ICVIfuvMLySVEdvCv0CiezIssnPo=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=QZcCEpXeiPNKBiMjjywV9TaLIW4JKg5JaBiuwOf/3xvuLSmfFPNTJXKUFxRfTHxRn KtyzZUCRHeqrj7YD9egmxo/I8i2VxHSNhJSLNxldk+bQoePMynJNPbPYLPsFRHmgSN P8cFM1G7JNLYJ5i/7xp3yzOPcyCXtsIXgd74vl2o= Message-ID: Date: Fri, 3 Jul 2026 10:06:19 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/5] arm64: cpufeature: Detect BBML3 based on MMFR2 ID To: Mark Rutland , Linu Cherian Cc: Catalin Marinas , Will Deacon , Ryan Roberts , Kevin Brodsky , Suzuki K Poulose , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20260701094131.677636-1-linu.cherian@arm.com> <20260701094131.677636-3-linu.cherian@arm.com> Content-Language: en-US From: Anshuman Khandual In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 02/07/26 4:15 PM, Mark Rutland wrote: > On Wed, Jul 01, 2026 at 03:11:28PM +0530, Linu Cherian wrote: >> Add MMFR2 ID based BBML3 feature detection, so >> that compliant cpus doesn't need to be added to the >> midr list. >> >> Signed-off-by: Linu Cherian >> --- >> arch/arm64/kernel/cpufeature.c | 14 +++++++------- >> arch/arm64/tools/sysreg | 1 + >> 2 files changed, 8 insertions(+), 7 deletions(-) >> >> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c >> index 9986eb7b379c..d754b1b7da77 100644 >> --- a/arch/arm64/kernel/cpufeature.c >> +++ b/arch/arm64/kernel/cpufeature.c >> @@ -2133,6 +2133,7 @@ static bool hvhe_possible(const struct arm64_cpu_capabilities *entry, >> >> bool cpu_supports_bbml3(void) >> { >> + u64 mmfr2; >> /* CPUs that support BBML3 but dont advertise through MMFR2 ID */ >> static const struct midr_range supports_bbml3_list[] = { >> MIDR_REV_RANGE(MIDR_CORTEX_X4, 0, 3, 0xf), >> @@ -2144,15 +2145,14 @@ bool cpu_supports_bbml3(void) >> {} >> }; >> >> - if (!is_midr_in_range_list(supports_bbml3_list)) >> - return false; >> + if (is_midr_in_range_list(supports_bbml3_list)) >> + return true; >> >> - /* >> - * We currently ignore the ID_AA64MMFR2_EL1 register, and only care >> - * about whether the MIDR check passes. >> - */ >> + mmfr2 = __read_sysreg_by_encoding(SYS_ID_AA64MMFR2_EL1); >> + if (SYS_FIELD_GET(ID_AA64MMFR2_EL1, BBM, mmfr2) == ID_AA64MMFR2_EL1_BBM_3) >> + return true; > > This needs to be '>=', so that if there's a future BBML4, we correctly > detect that CPUs with BBML4 also have the BBML3 behaviour. That's right. > > It would also be better to check the ID field first, before falling back > to the MIDR check. That way a reader can more clearly see that > supports_bbml3_list catches older parts that don't advertised BBML3, and > the comment above supports_bbml3_list would be clearer. Flipping the check order makes things clearer. > > With those changes, this looks sane to me. > > Mark. > >> >> - return true; >> + return false; >> } >> >> static bool has_bbml3(const struct arm64_cpu_capabilities *caps, int scope) >> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg >> index bc1788b1662b..082256ec3bf9 100644 >> --- a/arch/arm64/tools/sysreg >> +++ b/arch/arm64/tools/sysreg >> @@ -2259,6 +2259,7 @@ UnsignedEnum 55:52 BBM >> 0b0000 0 >> 0b0001 1 >> 0b0010 2 >> + 0b0011 3 >> EndEnum >> UnsignedEnum 51:48 TTL >> 0b0000 NI >> -- >> 2.43.0 >> Please move above tools/sysreg change into a separate patch as an update for existing ID_AA64MMFR2_EL1 definition.