Re: [PATCH DO NOT MERGE v6 17/18] arm64: dts: ti: k3-am62: New GPU binding details

[Matt Coster <Matt.Coster@imgtec.com>]

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On 10/04/2025 10:55, Matt Coster wrote:
> Use the new compatible string introduced earlier (in "dt-bindings: gpu:
> img: More explicit compatible strings") and add a name to the single power
> domain for this GPU (introduced in "dt-bindings: gpu: img: Power domain
> details").

Hi Nishanth, Vignesh & Tero,

Now that P1-16 have landed in a DRM tree, what would be required to get
this and the subsequent patch landed? Can they be reviewed and applied
as-is, or would you like me to send them as a separate series?

Cheers,
Matt

> 
> Signed-off-by: Matt Coster <matt.coster@imgtec.com>
> ---
> Changes in v6:
> - None
> - Link to v5: https://lore.kernel.org/r/20250326-sets-bxs-4-64-patch-v1-v5-17-e4c46e8280a9@imgtec.com
> Changes in v5:
> - None
> - Link to v4: https://lore.kernel.org/r/20250320-sets-bxs-4-64-patch-v1-v4-17-d987cf4ca439@imgtec.com
> Changes in v4:
> - None
> - Link to v3: https://lore.kernel.org/r/20250310-sets-bxs-4-64-patch-v1-v3-17-143b3dbef02f@imgtec.com
> Changes in v3:
> - None
> - Link to v2: https://lore.kernel.org/r/20241118-sets-bxs-4-64-patch-v1-v2-7-3fd45d9fb0cf@imgtec.com
> Changes in v2:
> - None
> - Link to v1: https://lore.kernel.org/r/20241105-sets-bxs-4-64-patch-v1-v1-7-4ed30e865892@imgtec.com
> ---
>  arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
> index 7d355aa73ea2116723735f70b9351cefcd8bc118..d17b25cae196b08d24adbe7c913ccaba7eed37eb 100644
> --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
> @@ -691,12 +691,14 @@ ospi0: spi@fc40000 {
>         };
> 
>         gpu: gpu@fd00000 {
> -               compatible = "ti,am62-gpu", "img,img-axe";
> +               compatible = "ti,am62-gpu", "img,img-axe-1-16m", "img,img-axe",
> +                            "img,img-rogue";
>                 reg = <0x00 0x0fd00000 0x00 0x20000>;
>                 clocks = <&k3_clks 187 0>;
>                 clock-names = "core";
>                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
>                 power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>;
> +               power-domain-names = "a";
>         };
> 
>         cpsw3g: ethernet@8000000 {
> 
> --
> 2.49.0
> 


-- 
Matt Coster
E: matt.coster@imgtec.com

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