From: Jinjie Ruan <ruanjinjie@huawei.com>
To: Will Deacon <will@kernel.org>, <linux-arm-kernel@lists.infradead.org>
Cc: <linux-kernel@vger.kernel.org>, Arnd Bergmann <arnd@arndb.de>,
Ard Biesheuvel <ardb@kernel.org>,
Ada Couprie Diaz <ada.coupriediaz@arm.com>,
David Hildenbrand <david@kernel.org>,
Catalin Marinas <catalin.marinas@arm.com>,
Vladimir Murzin <vladimir.murzin@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
Mostafa Saleh <smostafa@google.com>,
Lorenzo Stoakes <ljs@kernel.org>,
Oliver Upton <oupton@kernel.org>,
Linus Walleij <linusw@kernel.org>, Marc Zyngier <maz@kernel.org>
Subject: Re: [PATCH 01/21] arm64: entry: Defer setting of TPIDRRO_EL0 until exit to userspace
Date: Fri, 11 Sep 2026 15:53:36 +0800 [thread overview]
Message-ID: <f1675130-c72e-4c11-b2bf-daec44f02b29@huawei.com> (raw)
In-Reply-To: <20260907164247.17223-2-will@kernel.org>
在 2026/9/8 0:42, Will Deacon 写道:
> In preparation for using TPIDRRO_EL0 to point at 'current' while running
> inside the kernel, defer its userspace initialisation from the
> context-switch patch to exception return. This has the added benefit of
> not having to worry about keeping the in-memory value and the register
> value in-sync during preemptible sections.
>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Signed-off-by: Will Deacon <will@kernel.org>
> ---
> arch/arm64/kernel/asm-offsets.c | 1 +
> arch/arm64/kernel/entry.S | 4 +++-
> arch/arm64/kernel/process.c | 16 +---------------
> arch/arm64/kernel/sys_compat.c | 7 -------
> 4 files changed, 5 insertions(+), 23 deletions(-)
>
> diff --git a/arch/arm64/kernel/asm-offsets.c b/arch/arm64/kernel/asm-offsets.c
> index 9c853ed3ceab..6038ab3beb25 100644
> --- a/arch/arm64/kernel/asm-offsets.c
> +++ b/arch/arm64/kernel/asm-offsets.c
> @@ -42,6 +42,7 @@ int main(void)
> #endif
> BLANK();
> DEFINE(THREAD_CPU_CONTEXT, offsetof(struct task_struct, thread.cpu_context));
> + DEFINE(THREAD_TP_VALUE, offsetof(struct task_struct, thread.uw.tp_value));
> DEFINE(THREAD_SCTLR_USER, offsetof(struct task_struct, thread.sctlr_user));
> #ifdef CONFIG_ARM64_PTR_AUTH
> DEFINE(THREAD_KEYS_USER, offsetof(struct task_struct, thread.keys_user));
> diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
> index f63049ac32dc..59f045e496ec 100644
> --- a/arch/arm64/kernel/entry.S
> +++ b/arch/arm64/kernel/entry.S
> @@ -47,7 +47,6 @@
> b .Lskip_tramp_vectors_cleanup\@
> .if \regsize == 64
> mrs x30, tpidrro_el0
> - msr tpidrro_el0, xzr
> .else
> mov x30, xzr
> .endif
> @@ -360,9 +359,12 @@ alternative_else_nop_endif
> .if \el == 0
> ldr x23, [sp, #S_SP] // load return stack pointer
> msr sp_el0, x23
> + msr tpidrro_el0, xzr
> tst x22, #PSR_MODE32_BIT // native task?
> b.eq 3f
>
> + ldr x0, [tsk, #THREAD_TP_VALUE]
> + msr tpidrro_el0, x0
Reviewed-by: Jinjie Ruan <ruanjinjie@huawei.com>
> #ifdef CONFIG_ARM64_ERRATUM_845719
> alternative_if ARM64_WORKAROUND_845719
> #ifdef CONFIG_PID_IN_CONTEXTIDR
> diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c
> index 581f80e9b9b7..bfdc12166895 100644
> --- a/arch/arm64/kernel/process.c
> +++ b/arch/arm64/kernel/process.c
> @@ -256,17 +256,8 @@ static void tls_thread_flush(void)
> if (system_supports_tpidr2())
> write_sysreg_s(0, SYS_TPIDR2_EL0);
>
> - if (is_compat_task()) {
> + if (is_compat_task())
> current->thread.uw.tp_value = 0;
> -
> - /*
> - * We need to ensure ordering between the shadow state and the
> - * hardware state, so that we don't corrupt the hardware state
> - * with a stale shadow state during context switch.
> - */
> - barrier();
> - write_sysreg(0, tpidrro_el0);
> - }
> }
>
> static void flush_tagged_addr_state(void)
> @@ -531,11 +522,6 @@ static void tls_thread_switch(struct task_struct *next)
> {
> tls_preserve_current_state();
>
> - if (is_compat_thread(task_thread_info(next)))
> - write_sysreg(next->thread.uw.tp_value, tpidrro_el0);
> - else
> - write_sysreg(0, tpidrro_el0);
> -
> write_sysreg(*task_user_tls(next), tpidr_el0);
> if (system_supports_tpidr2())
> write_sysreg_s(next->thread.tpidr2_el0, SYS_TPIDR2_EL0);
> diff --git a/arch/arm64/kernel/sys_compat.c b/arch/arm64/kernel/sys_compat.c
> index 0451f96c2c3f..59eee301c6f4 100644
> --- a/arch/arm64/kernel/sys_compat.c
> +++ b/arch/arm64/kernel/sys_compat.c
> @@ -89,13 +89,6 @@ long compat_arm_syscall(struct pt_regs *regs, int scno)
>
> case __ARM_NR_compat_set_tls:
> current->thread.uw.tp_value = regs->regs[0];
> -
> - /*
> - * Protect against register corruption from context switch.
> - * See comment in tls_thread_flush.
> - */
> - barrier();
> - write_sysreg(regs->regs[0], tpidrro_el0);
> return 0;
>
> default:
next prev parent reply other threads:[~2026-09-11 7:53 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-07 16:42 [PATCH 00/21] arm64: Move overflow sp into SP_EL1 and kernel sp into SP_EL0 Will Deacon
2026-09-07 16:42 ` [PATCH 01/21] arm64: entry: Defer setting of TPIDRRO_EL0 until exit to userspace Will Deacon
2026-09-11 7:53 ` Jinjie Ruan [this message]
2026-09-07 16:42 ` [PATCH 02/21] arm64: entry: Only check for stack overflow on exceptions from EL1 Will Deacon
2026-09-07 16:42 ` [PATCH 03/21] arm64: stackprotector: Temporarily disable per-task stackprotector Will Deacon
2026-09-07 16:42 ` [PATCH 04/21] arm64: bpf: Add support for generating reads of TPIDRRO_EL0 Will Deacon
2026-09-07 16:42 ` [PATCH 05/21] KVM: arm64: Protect TPIDRRO_EL0 across guest entry/exit Will Deacon
2026-09-07 16:42 ` [PATCH 06/21] arm64: Store 'current' in TPIDRRO_EL0 instead of SP_EL0 Will Deacon
2026-09-08 13:19 ` David Laight
2026-09-11 12:57 ` Will Deacon
2026-09-07 16:42 ` [PATCH 07/21] selftests/bpf: arm64: Use TPIDRRO_EL0 instead of SP_EL0 for 'current' Will Deacon
2026-09-07 16:42 ` [PATCH 08/21] scripts/gdb: " Will Deacon
2026-09-07 16:42 ` [PATCH 09/21] arm64: stackprotector: Re-enable per-task stackprotector Will Deacon
2026-09-07 16:42 ` [PATCH 10/21] arm64: percpu: Specialise set_my_cpu_offset() for the primary CPU Will Deacon
2026-09-07 16:42 ` [PATCH 11/21] arm64: percpu: Annotate __kern_my_cpu_offset() as '__always_inline' Will Deacon
2026-09-07 16:42 ` [PATCH 12/21] KVM: arm64: Preserve handler/thread bit of EL1 mode in __finalise_el2() Will Deacon
2026-09-07 16:42 ` [PATCH 13/21] arm64: sdei: Guard most of asm/sdei.h with CONFIG_ARM_SDE_INTERFACE Will Deacon
2026-09-07 16:42 ` [PATCH 14/21] arm64: sdei: Support SDEI events from kernel handler and thread modes Will Deacon
2026-09-07 16:42 ` [PATCH 15/21] arm64: entry: Point SP_EL0 at the overflow stack Will Deacon
2026-09-07 16:42 ` [PATCH 16/21] arm64: entry: Implement EL1t exception handlers for " Will Deacon
2026-09-07 16:42 ` [PATCH 17/21] arm64: entry: Use SPSel to switch to " Will Deacon
2026-09-07 16:42 ` [PATCH 18/21] arm64: entry: Split up kernel_ventry macro into separate helper macros Will Deacon
2026-09-07 16:42 ` [PATCH 19/21] arm64: entry: The great stack switcheroo Will Deacon
2026-09-08 11:30 ` Will Deacon
2026-09-07 16:42 ` [PATCH 20/21] arm64: tracing: Advertise a mode of EL1t in synthetic kernel regs Will Deacon
2026-09-07 16:42 ` [PATCH 21/21] arm64: Rename 'overflow_stack' and OVERFLOW_STACK_SIZE Will Deacon
2026-09-09 10:39 ` [PATCH 00/21] arm64: Move overflow sp into SP_EL1 and kernel sp into SP_EL0 Vladimir Murzin
2026-09-09 11:29 ` Will Deacon
2026-09-10 13:49 ` Vladimir Murzin
2026-09-11 12:57 ` Will Deacon
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